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| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-06-23 11:25:41 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-28 13:38:20 +0000 |
| commit | 396035114149f92d69b1ebe3ecb661ba59181e7f (patch) | |
| tree | 102aeb9268d3c16a66e6e201c47ff4a504266c20 /src/ec/roda/it8518/Makefile.inc | |
| parent | 32ed65611d796d507dd004d9a2d97d38b3c2ce7e (diff) | |
soc/mediatek/mt8192: Do dramc pre-settings before calibration
Before calibration, dramc resets the delay of each PHY IO, calculates
TX path and sets CKE to be rank independent.
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/ec/roda/it8518/Makefile.inc')
0 files changed, 0 insertions, 0 deletions