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authorV Sowmya <v.sowmya@intel.com>2020-11-13 11:48:52 +0530
committerFurquan Shaikh <furquan@google.com>2020-11-18 01:26:37 +0000
commit0759346cd6c0dcfd300eeca216e0a2d2ed76a827 (patch)
treea400dc9848e03abb205f9d3e1c37ffaca7653d6c /src/ec/purism
parentf2e8a7ae6bb228d43d88b4cd75ee33e0b72d36ab (diff)
mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update
This patch modifies flash layout to add ME_RW_A/B to add the CSE RW blob and also enable the CSE RW update feature for JSLRVP BUG=b:169077783 TEST= Built for jslrvp. Verified that CSE RW and metadata files are included in cbfs. Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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