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authorFurquan Shaikh <furquan@google.com>2014-11-21 15:54:39 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-10 20:47:52 +0200
commit14b444b83be0fe3c3a7fc524265e64d535018049 (patch)
treec74383d3d076b96ec921b858bd1bd5a3b8e92460 /src/ec/lenovo
parent9482498003d500db6aced4c94bf4ab3485cab18e (diff)
arm64: No need of invalidating cache line for secondary CPU stack
With support for initializing registers based on values saved by primary CPU, we no longer need to invalidate secondary CPU stack cache lines. Before jumping to C environment, we enable caching and update the required registers. BUG=chrome-os-partner:33962 BRANCH=None TEST=Compiles and boots both CPU0 and CPU1 on ryu. Change-Id: Ifee36302b5de25b909b4570a30ada8ecd742ab82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a0403d06b89dae30b7520747501b0521d16a6db Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I738250f948e912725264cba3e389602af7510e3e Original-Reviewed-on: https://chromium-review.googlesource.com/231563 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9541 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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