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| author | Maximilian Brune <maximilian.brune@9elements.com> | 2024-04-15 18:17:54 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-07-01 13:44:19 +0000 |
| commit | 99bed46c5d5470a7052a477c7b7edae24942165e (patch) | |
| tree | 25255de7566f162ca778c377318636eba42f4330 /src/ec/lenovo/pmh7/chip.h | |
| parent | c693e92c7482557a4685c6ce8dda0db5cfdd734f (diff) | |
commonlib/bsd/lz4_wrapper.c: Fix misaligned access
Currently the HiFive Unleashed produces the following exception:
[DEBUG] Exception: Load address misaligned
[DEBUG] Hart ID: 0
[DEBUG] Previous mode: machine
[DEBUG] Bad instruction pc: 0x080010d0
[DEBUG] Bad address: 0x08026ab3
[DEBUG] Stored ra: 0x080010c8
[DEBUG] Stored sp: 0x08010cc8
The coreboot LZ4 decompression code does some misaligned access during
decompression which the FU540 apparently does not support in SRAM.
Make the compiler generate code that adheres to natural alignment by
fixing the LZ4_readLE16() function and creating LZ4_readLE32().
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81910
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec/lenovo/pmh7/chip.h')
0 files changed, 0 insertions, 0 deletions