diff options
author | Bora Guvendik <bora.guvendik@intel.com> | 2019-12-16 16:51:38 -0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-19 17:48:15 +0000 |
commit | 3280b7672907cd70609f90010a653fa47b4e7c85 (patch) | |
tree | 28f2ea177a29fe6d62c04c2cec3ec38180f0a760 /src/ec/google | |
parent | 25eb1b3149ccb3f1f0599b9bc05c5b5f196d303d (diff) |
storage/mmc: Fix wrong frequency setting for HS speed mode
Emmc spec, JEDEC Standard No. 84-B51, section 6.6.2.3, selection
flow of HS400 using Enhanced Strobe states that host should change
frequency to ≤ 52MHz when switching to HS speed mode first. In
current code, mmc_select_hs400() calls mmc_select_hs() to do this,
however caps are not cleared, so when switching from HS200 to HS400,
caps will still have DRVR_CAP_HS200, and mmc_recalculate_clock() will
set 200Mhz instead of ≤ 52MHz. As a result, switching to HS400 will
intermittently fail.
BUG=b:140124451
TEST=Switch speed from HS200 to HS400 on WHL RVP.
Change-Id: Ie639c7616105cca638417d7bc1db95b561afb7af
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37775
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec/google')
0 files changed, 0 insertions, 0 deletions