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authorBora Guvendik <bora.guvendik@intel.com>2017-09-13 18:39:16 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-19 23:19:53 +0000
commit67fb347668eb9aa85936daf140af72c4384cf5f5 (patch)
tree75aba31613b80177d1d032a4db871182134009f3 /src/ec/google
parenta0e0b054bd086d09d0577c6c1548acae45bb3176 (diff)
soc/intel/cannonlake: Add PCIE IRQs
Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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