ec/google/chromeec: Provide EC access for Retimer firmware update

Kernel needs to access EC RFWU entry in order to retrieve from EC about
port and mux info and set EC operations like modes change. This change
provides EC RFWU path and update for Retimer driver usage.

BUG=b:162528867
TEST=Booted to kernel and verified EC RFWU path from ACPI SSDT table.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3817d93cfdeedf15825dab6c537b151fd063338b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49257
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c
index fff395411c..bcecd8920b 100644
--- a/src/ec/google/chromeec/ec_acpi.c
+++ b/src/ec/google/chromeec/ec_acpi.c
@@ -7,6 +7,7 @@
 #include <acpi/acpigen_usb.h>
 #include <console/console.h>
 #include <drivers/usb/acpi/chip.h>
+#include <drivers/intel/usb4/retimer/retimer.h>
 #include <ec/google/common/dptf.h>
 
 #include "chip.h"
@@ -235,3 +236,30 @@ void google_chromeec_fill_ssdt_generator(const struct device *dev)
 	fill_ssdt_typec_device(dev);
 	fill_ssdt_ps2_keyboard(dev);
 }
+
+const char *ec_retimer_fw_update_path(void)
+{
+	return "\\_SB_.PCI0.LPCB.EC0_.RFWU";
+}
+
+void ec_retimer_fw_update(void *arg)
+{
+	const char *RFWU = ec_retimer_fw_update_path();
+
+	/*
+	 * Get information to set retimer info from Arg3[0]
+	 * Local0 = DeRefOf (Arg3[0])
+	 */
+	acpigen_get_package_op_element(ARG3_OP, 0, LOCAL0_OP);
+
+	/*
+	 * Write the EC RAM for Retimer Upgrade
+	 * RFWU = LOCAL0
+	 */
+	acpigen_write_store();
+	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_emit_namestring(RFWU);
+
+	/* Return (Zero) */
+	acpigen_write_return_integer(0);
+}