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authorAaron Durbin <adurbin@chromium.org>2014-01-09 11:17:37 -0600
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-13 16:11:25 +0200
commit19edc3a2e53eb54994a99ca8a868480badcbf227 (patch)
treec2c02125913d00ebf5aaddae673a3c4a18ab26a6 /src/ec/google/chromeec
parent8f31ecf28b9788d007be746fc85160cb6e91c1ca (diff)
baytrail: clear the pmc wake status registers
The PMC in baytrail maintains an additional set wake status in memory-mapped registers. If these bits aren't cleared the device won't be able to go to S5 or S3 without being immediately woken up. Therefore clear these registers. BUG=chrome-os-partner:24913 BRANCH=rambi,squawks TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work correctly. Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181984 Reviewed-on: http://review.coreboot.org/5034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/ec/google/chromeec')
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