aboutsummaryrefslogtreecommitdiff
path: root/src/ec/google/chromeec/ec.h
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@chromium.org>2017-10-17 15:06:37 -0700
committerFurquan Shaikh <furquan@google.com>2017-10-19 00:43:45 +0000
commitdd825fe73ec9832ff100955cf564dea68cee2d81 (patch)
treee941c884a44db4bacba5b7820494613ee3706969 /src/ec/google/chromeec/ec.h
parent7284efe594114c7bcc933550ade9f728cbf0ca8f (diff)
soc/intel/skylake: Probe XHCI for wake source for Internal PME
If GPE_STS indicates that the wake source is internal PME, but none of the controllers have the PME_STS bit set, then try probing individual XHCI ports to see if one of those was a wake source. In some cases e.g. gsmi logging with S0ix, pci_pm_resume_noirq runs before gsmi callback and clears PME_STS_BIT in controller register. In such cases, xhci port status might provide a better idea about the wake source. BUG=b:67874513 Change-Id: I841bb2abccfa9bd6553c1513e88a6306b40315e4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/ec/google/chromeec/ec.h')
0 files changed, 0 insertions, 0 deletions