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authorLijian Zhao <lijian.zhao@intel.com>2017-07-14 11:09:10 -0700
committerAaron Durbin <adurbin@chromium.org>2017-08-15 20:21:31 +0000
commit2f764f7dfe95e318057a241d8136fc866ebfed60 (patch)
tree55510c6083a6cf4f650a748923ae1b1addc168f5 /src/ec/google/chromeec/ec.c
parent8465a81e81dfb2ed1fc24b9cf053b09d86fa5163 (diff)
soc/intel/cannonlake: Call into FSP siliconinit
The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. This patch was merged too early, and reverted. Originally reviewed on https://review.coreboot.org/#/c/20581 Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20687 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/ec/google/chromeec/ec.c')
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