Add support for Google ChromeEC

Google ChromeEC is an EC with completely open source firmware.
See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary
for the EC firmware source code (aka more information about the ChromeEC)

This patch adds support for the ChromeEC on coreboot's side.

Great thanks to the ChromeEC team for this amazing work. It's another
important milestone towards a free and open firmware stack on modern
hardware.

Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec
Signed-off-by: Stefan Reinauer <reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/2481
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

4 files changed, 648 insertions, 0 deletions

diff --git a/src/ec/google/chromeec/acpi/ac.asl b/src/ec/google/chromeec/acpi/ac.asl
new file mode 100644
index 0000000000..34b9080fa4
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/ac.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Scope (EC0)
+
+Device (AC)
+{
+	Name (_HID, "ACPI0003")
+	Name (_PCL, Package () { \_SB })
+
+	Method (_PSR)
+	{
+		Return (ACEX)
+	}
+
+	Method (_STA)
+	{
+		Return (0x0F)
+	}
+}
diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl
new file mode 100644
index 0000000000..341911c372
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/battery.asl
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Scope (EC0)
+
+Device (BAT0)
+{
+	Name (_HID, EISAID ("PNP0C0A"))
+	Name (_UID, 1)
+	Name (_PCL, Package () { \_SB })
+
+	Name (PBIF, Package () {
+		0x00000001,  // 0x00: Power Unit: mAh
+		0xFFFFFFFF,  // 0x01: Design Capacity
+		0xFFFFFFFF,  // 0x02: Last Full Charge Capacity
+		0x00000001,  // 0x03: Battery Technology: Rechargeable
+		0xFFFFFFFF,  // 0x04: Design Voltage
+		0x00000003,  // 0x05: Design Capacity of Warning
+		0xFFFFFFFF,  // 0x06: Design Capacity of Low
+		0x00000001,  // 0x07: Capacity Granularity 1
+		0x00000001,  // 0x08: Capacity Granularity 2
+		"",          // 0x09: Model Number
+		"",          // 0x0a: Serial Number
+		"LION",      // 0x0b: Battery Type
+		""           // 0x0c: OEM Information
+	})
+
+	Name (PBIX, Package () {
+		0x00000000,  // 0x00: Revision
+		0x00000001,  // 0x01: Power Unit: mAh
+		0xFFFFFFFF,  // 0x02: Design Capacity
+		0xFFFFFFFF,  // 0x03: Last Full Charge Capacity
+		0x00000001,  // 0x04: Battery Technology: Rechargeable
+		0xFFFFFFFF,  // 0x05: Design Voltage
+		0x00000003,  // 0x06: Design Capacity of Warning
+		0xFFFFFFFF,  // 0x07: Design Capacity of Low
+		0x00000000,  // 0x08: Cycle Count
+		0x00018000,  // 0x09: Measurement Accuracy (98.3%?)
+		0x000001F4,  // 0x0a: Max Sampling Time (500ms)
+		0x0000000a,  // 0x0b: Min Sampling Time (10ms)
+		0xFFFFFFFF,  // 0x0c: Max Averaging Interval
+		0xFFFFFFFF,  // 0x0d: Min Averaging Interval
+		0x00000001,  // 0x0e: Capacity Granularity 1
+		0x00000001,  // 0x0f: Capacity Granularity 2
+		"",          // 0x10 Model Number
+		"",          // 0x11: Serial Number
+		"LION",      // 0x12: Battery Type
+		""           // 0x13: OEM Information
+	})
+
+	Name (PBST, Package () {
+		0x00000000,  // 0x00: Battery State
+		0xFFFFFFFF,  // 0x01: Battery Present Rate
+		0xFFFFFFFF,  // 0x02: Battery Remaining Capacity
+		0xFFFFFFFF,  // 0x03: Battery Present Voltage
+	})
+	Name (BSTP, Zero)
+
+	// Workaround for full battery status, enabled by default
+	Name (BFWK, One)
+
+	// Method to enable full battery workaround
+	Method (BFWE)
+	{
+		Store (One, BFWK)
+	}
+
+	// Method to disable full battery workaround
+	Method (BFWD)
+	{
+		Store (Zero, BFWK)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (BTEX) {
+			Return (0x1F)
+		} Else {
+			Return (0x0F)
+		}
+	}
+
+	Method (_BIF, 0, Serialized)
+	{
+		// Last Full Charge Capacity
+		Store (BTDF, Index (PBIF, 2))
+
+		// Design Voltage
+		Store (BTDV, Index (PBIF, 4))
+
+		// Design Capacity
+		Store (BTDA, Local0)
+		Store (Local0, Index (PBIF, 1))
+
+		// Design Capacity of Warning
+		Divide (Multiply (Local0, DWRN), 100, Local1, Local2)
+		Store (Local2, Index (PBIF, 5))
+
+		// Design Capacity of Low
+		Divide (Multiply (Local0, DLOW), 100, Local1, Local2)
+		Store (Local2, Index (PBIF, 6))
+
+		// Get battery info from mainboard
+		Store (ToString(BMOD), Index (PBIF, 9))
+		Store (ToString(BSER), Index (PBIF, 10))
+		Store (ToString(BMFG), Index (PBIF, 12))
+
+		Return (PBIF)
+	}
+
+	// Extended Battery info method is disabled for now due to
+	// a bug in the Linux kernel: http://crosbug.com/28747
+	Method (XBIX, 0, Serialized)
+	{
+		// Last Full Charge Capacity
+		Store (BTDF, Index (PBIX, 3))
+
+		// Design Voltage
+		Store (BTDV, Index (PBIX, 5))
+
+		// Design Capacity
+		Store (BTDA, Local0)
+		Store (Local0, Index (PBIX, 2))
+
+		// Design Capacity of Warning
+		Divide (Multiply (Local0, DWRN), 100, Local1, Local2)
+		Store (Local2, Index (PBIX, 6))
+
+		// Design Capacity of Low
+		Divide (Multiply (Local0, DLOW), 100, Local1, Local2)
+		Store (Local2, Index (PBIX, 7))
+
+		// Cycle Count
+		Store (BTCC, Index (PBIX, 8))
+
+		// Get battery info from mainboard
+		Store (ToString(BMOD), Index (PBIX, 16))
+		Store (ToString(BSER), Index (PBIX, 17))
+		Store (ToString(BMFG), Index (PBIX, 19))
+
+		Return (PBIX)
+	}
+
+	Method (_BST, 0, Serialized)
+	{
+		//
+		// 0: BATTERY STATE
+		//
+		// bit 0 = discharging
+		// bit 1 = charging
+		// bit 2 = critical level
+		//
+		Store (Zero, Local1)
+
+		// Check if AC is present
+		If (ACEX) {
+			If (BFCG) {
+				Store (0x02, Local1)
+			} ElseIf (BFDC) {
+				Store (0x01, Local1)
+			}
+		} Else {
+			// Always discharging when on battery power
+			Store (0x01, Local1)
+		}
+
+		// Check for critical battery level
+		If (BFCR) {
+			Or (Local1, 0x04, Local1)
+		}
+		Store (Local1, Index (PBST, 0))
+
+		// Notify if battery state has changed since last time
+		If (LNotEqual (Local1, BSTP)) {
+			Store (Local1, BSTP)
+			Notify (BAT0, 0x80)
+		}
+
+		//
+		// 1: BATTERY PRESENT RATE
+		//
+		Store (BTPR, Index (PBST, 1))
+
+		//
+		// 2: BATTERY REMAINING CAPACITY
+		//
+		Store (BTRA, Local1)
+		If (LAnd (BFWK, LAnd (ACEX, LNot (LAnd (BFDC, BFCG))))) {
+			// On AC power and battery is neither charging
+			// nor discharging.  Linux expects a full battery
+			// to report same capacity as last full charge.
+			// https://bugzilla.kernel.org/show_bug.cgi?id=12632
+			Store (BTDF, Local2)
+
+			// See if within ~3% of full
+			ShiftRight (Local2, 5, Local3)
+			If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+			          LLess (Local1, Add (Local2, Local3))))
+			{
+				Store (Local2, Local1)
+			}
+		}
+		Store (Local1, Index (PBST, 2))
+
+		//
+		// 3: BATTERY PRESENT VOLTAGE
+		//
+		Store (BTVO, Index (PBST, 3))
+
+		Return (PBST)
+	}
+}
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
new file mode 100644
index 0000000000..2fb8e7961c
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+Device (EC0)
+{
+	Name (_HID, EISAID ("PNP0C09"))
+	Name (_UID, 1)
+	Name (_GPE, Add(EC_SCI_GPI, 16))
+	Name (TOFS, EC_TEMP_SENSOR_OFFSET)
+	Name (TNOP, 0xFD)	// Thermal sensor has no power
+	Name (TBAD, 0xFE)	// Thermal sensor bad reading
+	Name (TNPR, 0xFF)	// Thermal sensor not present
+	Name (DWRN, 15)		// Battery capacity warning at 15%
+	Name (DLOW, 10)		// Battery capacity low at 10%
+
+	OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+	Field (ERAM, ByteAcc, Lock, Preserve)
+	{
+		Offset (0x00),
+		RAMV, 8,	// EC RAM Version
+		TSTB, 8,	// Test Byte
+		TSTC, 8,	// Complement of Test Byte
+		KBLV, 8,	// Keyboard Backlight
+	}
+
+	OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
+	Field (EMEM, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x00),
+		TIN0, 8,	// Temperature 0
+		TIN1, 8,	// Temperature 1
+		TIN2, 8,	// Temperature 2
+		TIN3, 8,	// Temperature 3
+		TIN4, 8,	// Temperature 4
+		TIN5, 8,	// Temperature 5
+		TIN6, 8,	// Temperature 6
+		TIN7, 8,	// Temperature 7
+		TIN8, 8,	// Temperature 8
+		TIN9, 8,	// Temperature 9
+		Offset (0x10),
+		FAN0, 16,	// Fan Speed 0
+		Offset (0x30),
+		LIDS, 1,	// Lid Switch State
+		PBTN, 1,	// Power Button Pressed
+		WPDI, 1,	// Write Protect Disabled
+		RECK, 1,	// Keyboard Initiated Recovery
+		RECD, 1,	// Dedicated Recovery Mode
+		Offset (0x40),
+		BTVO, 32,	// Battery Present Voltage
+		BTPR, 32,	// Battery Present Rate
+		BTRA, 32,	// Battery Remaining Capacity
+		ACEX, 1,	// AC Present
+		BTEX, 1,	// Battery Present
+		BFDC, 1,	// Battery Discharging
+		BFCG, 1,	// Battery Charging
+		BFCR, 1,	// Battery Level Critical
+		Offset (0x50),
+		BTDA, 32,	// Battery Design Capacity
+		BTDV, 32,	// Battery Design Voltage
+		BTDF, 32,	// Battery Last Full Charge Capacity
+		BTCC, 32,	// Battery Cycle Count
+		BMFG, 64,	// Battery Manufacturer String
+		BMOD, 64,	// Battery Model String
+		BSER, 64,	// Battery Serial String
+		BTYP, 64,	// Battery Type String
+	}
+
+	Method (TINS, 1, Serialized)
+	{
+		Switch (ToInteger (Arg0))
+		{
+			Case (0) { Return (TIN0) }
+			Case (1) { Return (TIN1) }
+			Case (2) { Return (TIN2) }
+			Case (3) { Return (TIN3) }
+			Case (4) { Return (TIN4) }
+			Case (5) { Return (TIN5) }
+			Case (6) { Return (TIN6) }
+			Case (7) { Return (TIN7) }
+			Case (8) { Return (TIN8) }
+			Case (9) { Return (TIN9) }
+			Default  { Return (TIN0) }
+		}
+	}
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16,
+			    EC_LPC_ADDR_ACPI_DATA,
+			    EC_LPC_ADDR_ACPI_DATA,
+			    0, 1)
+			IO (Decode16,
+			    EC_LPC_ADDR_ACPI_CMD,
+			    EC_LPC_ADDR_ACPI_CMD,
+			    0, 1)
+		})
+		Return (ECMD)
+	}
+
+	Method (_REG, 2, NotSerialized)
+	{
+		// Initialize AC power state
+		Store (ACEX, \PWRS)
+
+		// Initialize LID switch state
+		Store (LIDS, \LIDS)
+	}
+
+	// Lid Closed Event
+	Method (_Q01, 0, NotSerialized)
+	{
+		Store ("EC: LID CLOSE", Debug)
+		Store (LIDS, \LIDS)
+		Notify (\_SB.LID0, 0x80)
+	}
+
+	// Lid Open Event
+	Method (_Q02, 0, NotSerialized)
+	{
+		Store ("EC: LID OPEN", Debug)
+		Store (LIDS, \LIDS)
+		Notify (\_SB.LID0, 0x80)
+	}
+
+	// Power Button
+	Method (_Q03, 0, NotSerialized)
+	{
+		Store ("EC: POWER BUTTON", Debug)
+		Notify (\_SB.PWRB, 0x80)
+	}
+
+	// AC Connected
+	Method (_Q04, 0, NotSerialized)
+	{
+		Store ("EC: AC CONNECTED", Debug)
+		Store (ACEX, \PWRS)
+		Notify (AC, 0x80)
+		\PNOT ()
+	}
+
+	// AC Disconnected
+	Method (_Q05, 0, NotSerialized)
+	{
+		Store ("EC: AC DISCONNECTED", Debug)
+		Store (ACEX, \PWRS)
+		Notify (AC, 0x80)
+		\PNOT ()
+	}
+
+	// Battery Low Event
+	Method (_Q06, 0, NotSerialized)
+	{
+		Store ("EC: BATTERY LOW", Debug)
+		Notify (BAT0, 0x80)
+	}
+
+	// Battery Critical Event
+	Method (_Q07, 0, NotSerialized)
+	{
+		Store ("EC: BATTERY CRITICAL", Debug)
+		Notify (BAT0, 0x80)
+	}
+
+	// Battery Info Event
+	Method (_Q08, 0, NotSerialized)
+	{
+		Store ("EC: BATTERY INFO", Debug)
+		Notify (BAT0, 0x81)
+	}
+
+	// Thermal Treshold Event
+	Method (_Q09, 0, NotSerialized)
+	{
+		Store ("EC: THERMAL THRESHOLD", Debug)
+		Notify (\_TZ, 0x80)
+	}
+
+	// Thermal Overload Event
+	Method (_Q0A, 0, NotSerialized)
+	{
+		Store ("EC: THERMAL OVERLOAD", Debug)
+		Notify (\_TZ, 0x80)
+	}
+
+	// Thermal Event
+	Method (_Q0B, 0, NotSerialized)
+	{
+		Store ("EC: THERMAL", Debug)
+		Notify (\_TZ, 0x80)
+	}
+
+	// USB Charger
+	Method (_Q0C, 0, NotSerialized)
+	{
+		Store ("EC: USB CHARGER", Debug)
+	}
+
+	// Key Pressed
+	Method (_Q0D, 0, NotSerialized)
+	{
+		Store ("EC: KEY PRESSED", Debug)
+	}
+
+	#include "ac.asl"
+	#include "battery.asl"
+}
diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl
new file mode 100644
index 0000000000..56f0f185c6
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/superio.asl
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Chrome OS Embedded Controller interface
+ *
+ * Constants that should be defined:
+ *
+ * SIO_EC_MEMMAP_ENABLE     : Enable EC LPC memory map resources
+ * EC_LPC_ADDR_MEMMAP       : Base address of memory map range
+ * EC_MEMMAP_SIZE           : Size of memory map range
+ *
+ * SIO_EC_HOST_ENABLE       : Enable EC host command interface resources
+ * EC_LPC_ADDR_HOST_DATA    : EC host command interface data port
+ * EC_LPC_ADDR_HOST_CMD     : EC host command interface command port
+ * EC_LPC_ADDR_OLD_PARAM    : EC host command parameter range base (old)
+ * EC_OLD_PARAM_SIZE        : Parameter buffer size (old)
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+	Name (_UID, 0)
+	Name (_ADR, 0)
+
+#ifdef SIO_EC_MEMMAP_ENABLE
+	Device (ECMM) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, 1)
+		Name (_ADR, 0)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (0x0F)
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			FixedIO (EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			FixedIO (EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
+		})
+	}
+#endif
+
+#ifdef SIO_EC_HOST_ENABLE
+	Device (ECUI) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, 3)
+		Name (_ADR, 0)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (0x0F)
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			FixedIO (EC_LPC_ADDR_HOST_DATA, 1)
+			FixedIO (EC_LPC_ADDR_HOST_CMD, 1)
+			FixedIO (EC_LPC_ADDR_OLD_PARAM,
+				 EC_OLD_PARAM_SIZE)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			StartDependentFn (0, 0) {
+				FixedIO (EC_LPC_ADDR_HOST_DATA, 1)
+				FixedIO (EC_LPC_ADDR_HOST_CMD, 1)
+				FixedIO (EC_LPC_ADDR_OLD_PARAM,
+					 EC_OLD_PARAM_SIZE)
+			}
+			EndDependentFn ()
+		})
+	}
+#endif
+
+#ifdef SIO_EC_ENABLE_COM1
+	Device (COM1) {
+		Name (_HID, EISAID ("PNP0501"))
+		Name (_UID, 1)
+		Name (_ADR, 0)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (0x0F)
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			FixedIO (0x03F8, 0x08)
+			IRQNoFlags () {4}
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			StartDependentFn (0, 0) {
+				FixedIO (0x03F8, 0x08)
+				IRQNoFlags () {4}
+			}
+			EndDependentFn ()
+		})
+	}
+#endif
+
+#ifdef SIO_EC_ENABLE_PS2K
+	Device (PS2K)		// Keyboard
+	{
+		Name (_UID, 0)
+		Name (_ADR, 0)
+		Name (_HID, EISAID("PNP0303"))
+		Name (_CID, EISAID("PNP030B"))
+
+		Method (_STA, 0, NotSerialized) {
+			Return (0x0F)
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			FixedIO (0x60, 0x01)
+			FixedIO (0x64, 0x01)
+			IRQNoFlags () {1}
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			StartDependentFn (0, 0) {
+				FixedIO (0x60, 0x01)
+				FixedIO (0x64, 0x01)
+				IRQNoFlags () {1}
+			}
+			EndDependentFn ()
+		})
+	}
+#endif
+}