diff options
author | Stefan Reinauer <reinauer@chromium.org> | 2013-02-21 15:39:35 -0800 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-02-22 23:10:01 +0100 |
commit | d6682e88afc31f0d05f74638c28f6cc60fa2ba69 (patch) | |
tree | 3c9eb10fd9ad7a956fc6278815d8a6d23a764110 /src/ec/google/chromeec/acpi/superio.asl | |
parent | 50f313c8b2cae372d3d3868940c445aeb221ec1e (diff) |
Add support for Google ChromeEC
Google ChromeEC is an EC with completely open source firmware.
See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary
for the EC firmware source code (aka more information about the ChromeEC)
This patch adds support for the ChromeEC on coreboot's side.
Great thanks to the ChromeEC team for this amazing work. It's another
important milestone towards a free and open firmware stack on modern
hardware.
Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec
Signed-off-by: Stefan Reinauer <reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/2481
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/ec/google/chromeec/acpi/superio.asl')
-rw-r--r-- | src/ec/google/chromeec/acpi/superio.asl | 152 |
1 files changed, 152 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl new file mode 100644 index 0000000000..56f0f185c6 --- /dev/null +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Chrome OS Embedded Controller interface + * + * Constants that should be defined: + * + * SIO_EC_MEMMAP_ENABLE : Enable EC LPC memory map resources + * EC_LPC_ADDR_MEMMAP : Base address of memory map range + * EC_MEMMAP_SIZE : Size of memory map range + * + * SIO_EC_HOST_ENABLE : Enable EC host command interface resources + * EC_LPC_ADDR_HOST_DATA : EC host command interface data port + * EC_LPC_ADDR_HOST_CMD : EC host command interface command port + * EC_LPC_ADDR_OLD_PARAM : EC host command parameter range base (old) + * EC_OLD_PARAM_SIZE : Parameter buffer size (old) + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_MEMMAP_ENABLE + Device (ECMM) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + FixedIO (EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE) + }) + + Name (_PRS, ResourceTemplate () + { + FixedIO (EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE) + }) + } +#endif + +#ifdef SIO_EC_HOST_ENABLE + Device (ECUI) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 3) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + FixedIO (EC_LPC_ADDR_HOST_DATA, 1) + FixedIO (EC_LPC_ADDR_HOST_CMD, 1) + FixedIO (EC_LPC_ADDR_OLD_PARAM, + EC_OLD_PARAM_SIZE) + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + FixedIO (EC_LPC_ADDR_HOST_DATA, 1) + FixedIO (EC_LPC_ADDR_HOST_CMD, 1) + FixedIO (EC_LPC_ADDR_OLD_PARAM, + EC_OLD_PARAM_SIZE) + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_EC_ENABLE_COM1 + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + FixedIO (0x03F8, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + FixedIO (0x03F8, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif +} |