diff options
| author | Ben Chuang <benchuanggli@gmail.com> | 2023-08-21 11:01:04 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-08-30 09:05:39 +0000 |
| commit | df98e6b99b690f6e31cd5951af5acdcea4e11717 (patch) | |
| tree | 638caf4362273323264d9e9c7c76c80d9e6da344 /src/drivers | |
| parent | 9e57e9495090b8e2d3df51802e5c860f9b802d29 (diff) | |
drivers/genesyslogic/gl9750: Add invert write protect polarity
Add an option to invert write protect polarity for GL9750.
Change-Id: I5761f3066291a2400caecbecc79ae893f0a0c146
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77403
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/genesyslogic/gl9750/Kconfig | 5 | ||||
| -rw-r--r-- | src/drivers/genesyslogic/gl9750/gl9750.c | 4 | ||||
| -rw-r--r-- | src/drivers/genesyslogic/gl9750/gl9750.h | 2 |
3 files changed, 11 insertions, 0 deletions
diff --git a/src/drivers/genesyslogic/gl9750/Kconfig b/src/drivers/genesyslogic/gl9750/Kconfig index f3449b0d87..35dfc70441 100644 --- a/src/drivers/genesyslogic/gl9750/Kconfig +++ b/src/drivers/genesyslogic/gl9750/Kconfig @@ -6,3 +6,8 @@ config DRIVERS_GENESYSLOGIC_GL9750 regulators (3.3V-to-1.2V) and card power switch. Enabling this driver will disable L0s support, which will allow the device to enter the PCIe L1 link state. + +config DRIVERS_GENESYSLOGIC_GL9750_INVERT_WP + bool + depends on DRIVERS_GENESYSLOGIC_GL9750 + default n diff --git a/src/drivers/genesyslogic/gl9750/gl9750.c b/src/drivers/genesyslogic/gl9750/gl9750.c index c021eadf00..8c40c49d4f 100644 --- a/src/drivers/genesyslogic/gl9750/gl9750.c +++ b/src/drivers/genesyslogic/gl9750/gl9750.c @@ -22,6 +22,10 @@ static void gl9750_enable(struct device *dev) */ pci_and_config32(dev, CFG2, ~CFG2_L0S_SUPPORT); + if (CONFIG(DRIVERS_GENESYSLOGIC_GL9750_INVERT_WP)) + /* invert write protect polarity */ + pci_or_config32(dev, CFG1, CFG1_WP_INVERT); + /* Set Vendor Config to be non-configurable */ pci_and_config32(dev, CFG, ~CFG_EN); } diff --git a/src/drivers/genesyslogic/gl9750/gl9750.h b/src/drivers/genesyslogic/gl9750/gl9750.h index e446caefb9..e8041a050d 100644 --- a/src/drivers/genesyslogic/gl9750/gl9750.h +++ b/src/drivers/genesyslogic/gl9750/gl9750.h @@ -7,6 +7,8 @@ #define CFG 0x800 #define CFG_EN 0x1 +#define CFG1 0x844 +#define CFG1_WP_INVERT (0x1 << 31) #define CFG2 0x848 #define CFG2_L0S_SUPPORT (0x1 << 6) |