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authorArthur Heymans <arthur@aheymans.xyz>2021-01-23 15:09:48 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-01 08:45:37 +0000
commit5fc2bed629d2985807ae7784260837355cc9b8bb (patch)
tree53d12ecda9ce1295a5b5f3e1b598825ee4219e72 /src/drivers
parent129ed0a26470ab8b0bbecd77700c7016d14ef95d (diff)
drivers/intel/fsp2_0: Use CBFS_MCACHE when coreboot tears down CAR
TESTED on ocp/tiogapass. Change-Id: I30560149eeaec62af4c8a982815618be5546531c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/intel/fsp2_0/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 551b4b9060..14d97426c2 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -113,7 +113,7 @@ config FSP_S_FILE
config FSP_CAR
bool
default n
- select NO_CBFS_MCACHE
+ select NO_CBFS_MCACHE if !NO_FSP_TEMP_RAM_EXIT
help
Use FSP APIs to initialize & Tear Down the Cache-As-Ram