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authorSubrata Banik <subratabanik@google.com>2023-03-22 00:35:42 +0530
committerSubrata Banik <subratabanik@google.com>2023-03-23 05:54:28 +0000
commit30a011417fb227d8e1e78a6a47abd9ea332c00c7 (patch)
tree7128644516e689030e23c97a5a35e50d2f5616c1 /src/drivers
parent3f57a783c0844c326e7c3567e837b4456c02f8d9 (diff)
soc/intel: Rename IA common code module from `TOM` to `RAMTOP`
This patch renames all references of `top_of_ram` (TOM) in IA common `basecode` module (for example: functions, variables, Kconfig, Makefile and comments) with `ramtop` aka top_of_ram to make it more meaningful and to avoid conflicts with Intel SA chipset TOM registers. BUG=Able to build and boot google/rex with the same ~49ms savings in place. Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/intel/fsp2_0/memory_init.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 4f0dbf6148..6d25844b50 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -24,8 +24,8 @@
#include <types.h>
#include <vb2_api.h>
-#if CONFIG(SOC_INTEL_COMMON_BASECODE_TOM)
-#include <intelbasecode/tom.h>
+#if CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP)
+#include <intelbasecode/ramtop.h>
#endif
static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));
@@ -259,10 +259,10 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"FSPM_ARCH_UPD not found!\n");
- /* Early caching of TOM region if valid mrc cache data is found */
-#if (CONFIG(SOC_INTEL_COMMON_BASECODE_TOM))
+ /* Early caching of RAMTOP region if valid mrc cache data is found */
+#if (CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP))
if (arch_upd->NvsBufferPtr)
- early_tom_enable_cache_range();
+ early_ramtop_enable_cache_range();
#endif
/* Give SoC and mainboard a chance to update the UPD */