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authorMartin Roth <martinroth@google.com>2015-10-26 10:07:24 -0600
committerPatrick Georgi <pgeorgi@google.com>2015-10-28 19:22:04 +0100
commit158d00148f77569fc4a49176bcfeb4e0f990a1ff (patch)
tree8fc573d91f817c286aceab6a2a1bc00c3ef35037 /src/drivers
parent64d04806f9fcb3c740165153d53778a95f87eed1 (diff)
cpu/intel/fsp_model_206ax: Load microcode in coreboot
Intel's FSP 1.0 platforms are moving back to loading microcode in coreboot instead of in the FSP. Update the Ivy Bridge chips to be compatible. Change-Id: I4af155dea51e89ab9595b922c95ceade29a2dc52 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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