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authorLijian Zhao <lijian.zhao@intel.com>2018-12-06 22:53:44 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-09 09:29:28 +0000
commitffe4aededf4b62db3da3a61a99a3ff3d447f61e2 (patch)
tree57dd7abe3e8a031791bdda04170ff418de6edb96 /src/drivers
parentb1baa980ea2db879e6ec5ebf30bbdf16498d5afe (diff)
mb/google/sarien: Enable LAN clock source usage
FSP defined a special clock source usage 0x70 for PCH LAN device, update that to google sarien platform. BUG=b:120003760 TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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