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| author | Subrata Banik <subratabanik@google.com> | 2023-09-17 18:39:31 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-10-04 18:50:21 +0000 |
| commit | 1858903e780391cac0f37157f5de821b508d4e8d (patch) | |
| tree | d55d930c30b0f3600926a36a17c1bd76630d13e3 /src/drivers | |
| parent | b6b3c62ea188aacb4803bf6f00691a824bef98c5 (diff) | |
drivers/intel/gma: Update port select bit definitions
This commit updates the port select bit definitions for the
TRANS_DDI_FUNC_CTL registers in the Intel GMA driver to accommodate
the changes introduced since TGL SoC.
Specifically, the following changes were made:
- Updated the DDI select bit definitions from 3-bits (bit 28-30) to
4-bits (bit 27-30).
- Introduces `INTEL_GMA_VERSION_2` config to accommodate the port and
pipe related differences between previous generation GMA register
(TRANS_DDI_FUNC_CTL) to the current generation GMA register.
This commit backports the change from the following upstream patch:
https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-3-
lucas.demarchi@intel.com
BUG=b:299137940
TEST=Able to build and boot google/rex.
Change-Id: I815ffa90c2e235afd70baa7e3837e1f9af89b1b0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/drivers')
| -rw-r--r-- | src/drivers/intel/gma/Kconfig | 16 | ||||
| -rw-r--r-- | src/drivers/intel/gma/i915.h | 9 | ||||
| -rw-r--r-- | src/drivers/intel/gma/i915_reg.h | 14 |
3 files changed, 36 insertions, 3 deletions
diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index d1e16e2c3d..e6704f07bd 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -122,6 +122,22 @@ config INTEL_GMA_OPREGION_2_1 bool default n +config INTEL_GMA_VERSION_2 + bool + default n + help + Intel display port and pipe related register definitions have changed since + Tiger Lake SoC. This option enables support for the updated `TRANS_DDI_FUNC_CTL` + register definitions. + + SoCs that support Intel GMA Version 2 include: + * Alder Lake + * Meteor Lake + * Tiger Lake + + If you are unsure whether your SoC supports Intel GMA Version 2, it is safe to + disable this option. + if GFX_GMA || EARLY_GFX_GMA config GFX_GMA_DYN_CPU diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index 8e9fc904f2..5c341046f5 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -30,6 +30,12 @@ enum port { PORT_A = 0, PORT_B, PORT_C, +#if CONFIG(INTEL_GMA_VERSION_2) + PORT_USB_C1, + PORT_USB_C2, + PORT_USB_C3, + PORT_USB_C4, +#endif PORT_D, PORT_E, I915_NUM_PORTS @@ -39,6 +45,9 @@ enum pipe { PIPE_A = 0, PIPE_B, PIPE_C, +#if CONFIG(INTEL_GMA_VERSION_2) + PIPE_D, +#endif I915_NUM_PIPES }; diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 8a7ccf77fd..3d6cd45276 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -4181,9 +4181,17 @@ TRANS_DDI_FUNC_CTL_B) #define TRANS_DDI_FUNC_ENABLE (1UL<<31) /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ -#define TRANS_DDI_PORT_MASK (7<<28) -#define TRANS_DDI_SELECT_PORT(x) ((x)<<28) -#define TRANS_DDI_PORT_NONE (0<<28) +#if CONFIG(INTEL_GMA_VERSION_2) +#define TRANS_DDI_PORT_SHIFT 27 +#define TRANS_DDI_PORT_WIDTH 0xf +#define TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TRANS_DDI_PORT_SHIFT) +#else +#define TRANS_DDI_PORT_SHIFT 28 +#define TRANS_DDI_PORT_WIDTH 7 +#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) +#endif +#define TRANS_DDI_PORT_MASK (TRANS_DDI_PORT_WIDTH << TRANS_DDI_PORT_SHIFT) +#define TRANS_DDI_PORT_NONE (0 << TRANS_DDI_PORT_SHIFT) #define TRANS_DDI_MODE_SELECT_MASK (7<<24) #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) #define TRANS_DDI_MODE_SELECT_DVI (1<<24) |