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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-01-08 18:31:42 +0100
committerMartin Roth <martinroth@google.com>2018-02-20 20:44:43 +0000
commit27d34022588717dd5e5f9c309d362b645c2a9ffa (patch)
tree895df8d1ac35351b920e9086d6cbe6cfd5590cf3 /src/drivers
parent601197c768ea4a08802016f5b5aae6a9f22a751a (diff)
arch/riscv: Align trap_entry to 4 bytes, as required by spec
The RISC-V Privileged Architecture spec 1.10 requires that the address part of mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should be zero for now. Add the necessary alignment directive before trap_entry. Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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