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authorFurquan Shaikh <furquan@chromium.org>2017-05-25 00:16:15 -0700
committerFurquan Shaikh <furquan@google.com>2017-05-27 05:31:48 +0200
commitef8bb9136e9371753e50cb15b334c9d0f5c70930 (patch)
tree076404d59b2cb85ebd1c5d03a8141e3584aa7952 /src/drivers/xpowers
parent1cf7f86d92e7ea4a49d06e4aebf7213b259933fa (diff)
soc/intel/skylake: Add detailed information about PME wake sources
Add more fine-grained details about what device caused the PME wake event. This requires checking the PME status bit (bit 15) in PCI PM control and status register for the PCI device. BUG=b:37088992 TEST=Verifed that XHCI wake source was identified correctly: 135 | 2017-05-25 15:28:17 | ACPI Enter | S3 136 | 2017-05-25 15:28:26 | ACPI Wake | S3 137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0 Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19925 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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