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authorJeremy Compostella <jeremy.compostella@intel.com>2023-10-18 12:39:10 -0700
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-10-28 20:57:52 +0000
commite68650a656e185c7b056d62a79611ec2ad93e7dd (patch)
tree50ef4863daf1805d96385f2b532b202d7fed75c7 /src/drivers/tpm
parent648ed149a14c217bc84b0e4414fb49c8a626c7cb (diff)
vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header file
Export Power State Current 1, 2 and 3 Threshold configuration entries. BUG=b:308002192 Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e6 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
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