diff options
| author | Vinod Polimera <vpolimer@codeaurora.org> | 2020-06-23 16:23:06 +0530 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-09-10 00:24:42 +0000 |
| commit | c4e0b0a31378ae164ae2b6988c9779d96b627e84 (patch) | |
| tree | f33550cf690cdd47e8f3adc201bf2fef77eba3cd /src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h | |
| parent | c6880b3e9db4200aaeb3e5531a5b4d86d86ab0ef (diff) | |
sc7180: Add support for sn65dsi86 bridge
Add sn65dsi86 bridge driver to enable the eDP bridge.
Datasheet used : https://www.ti.com/lit/ds/sllseh2b/sllseh2b.pdf
Changes in V1:
- fix the dp lanes using mask
- separate out the refclk and hpd config to init function
Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h')
| -rw-r--r-- | src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h new file mode 100644 index 0000000000..83b940bbb4 --- /dev/null +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __TI_SN65DSI86BRIDGE_H +#define __TI_SN65DSI86BRIDGE_H + +#include <edid.h> + +enum dp_pll_clk_src { + SN65_SEL_12MHZ = 0x0, + SN65_SEL_19MHZ = 0x1, + SN65_SEL_26MHZ = 0x2, + SN65_SEL_27MHZ = 0x3, + SN65_SEL_38MHZ = 0x4, +}; + +void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk); +void sn65dsi86_bridge_configure(uint8_t bus, uint8_t chip, + struct edid *edid, uint32_t num_of_lines, + uint32_t dsi_bpp); +enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out); + +#endif |