commonlib: Move drivers/storage into commonlib/storage

Move drivers/storage into commonlib/storage to enable access by
libpayload and indirectly by payloads.

* Remove SD/MMC specific include files from include/device
* Remove files from drivers/storage
* Add SD/MMC specific include files to commonlib/include
* Add files to commonlib/storage
* Fix header file references
* Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver
* Add Kconfig source for commonlib/storage
* Rename *DEVICE* to *COMMONLIB*
* Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE*

TEST=Build and run on Galileo Gen2

Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 0 insertions, 281 deletions

diff --git a/src/drivers/storage/sdhci.h b/src/drivers/storage/sdhci.h
deleted file mode 100644
index 34a2972085..0000000000
--- a/src/drivers/storage/sdhci.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * Copyright 2011, Marvell Semiconductor Inc.
- * Lei Wen <leiwen@marvell.com>
- *
- * Copyright 2017 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __DRIVERS_STORAGE_SDHCI_H__
-#define __DRIVERS_STORAGE_SDHCI_H__
-
-#include <arch/io.h>
-#include <device/sd_mmc_ctrlr.h>
-
-/*
- * Controller registers
- */
-
-#define SDHCI_DMA_ADDRESS	0x00
-
-#define SDHCI_BLOCK_SIZE	0x04
-#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
-
-#define SDHCI_BLOCK_COUNT	0x06
-
-#define SDHCI_ARGUMENT		0x08
-
-#define SDHCI_TRANSFER_MODE	0x0C
-#define  SDHCI_TRNS_DMA		0x01
-#define  SDHCI_TRNS_BLK_CNT_EN	0x02
-#define  SDHCI_TRNS_ACMD12	0x04
-#define  SDHCI_TRNS_READ	0x10
-#define  SDHCI_TRNS_MULTI	0x20
-
-#define SDHCI_COMMAND		0x0E
-#define  SDHCI_CMD_RESP_MASK	0x03
-#define  SDHCI_CMD_CRC		0x08
-#define  SDHCI_CMD_INDEX	0x10
-#define  SDHCI_CMD_DATA		0x20
-#define  SDHCI_CMD_ABORTCMD	0xC0
-
-#define  SDHCI_CMD_RESP_NONE	0x00
-#define  SDHCI_CMD_RESP_LONG	0x01
-#define  SDHCI_CMD_RESP_SHORT	0x02
-#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
-
-#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
-#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
-
-#define SDHCI_RESPONSE		0x10
-
-#define SDHCI_BUFFER		0x20
-
-#define SDHCI_PRESENT_STATE	0x24
-#define  SDHCI_CMD_INHIBIT	0x00000001
-#define  SDHCI_DATA_INHIBIT	0x00000002
-#define  SDHCI_DOING_WRITE	0x00000100
-#define  SDHCI_DOING_READ	0x00000200
-#define  SDHCI_SPACE_AVAILABLE	0x00000400
-#define  SDHCI_DATA_AVAILABLE	0x00000800
-#define  SDHCI_CARD_PRESENT	0x00010000
-#define  SDHCI_CARD_STATE_STABLE	0x00020000
-#define  SDHCI_CARD_DETECT_PIN_LEVEL	0x00040000
-#define  SDHCI_WRITE_PROTECT	0x00080000
-
-#define SDHCI_HOST_CONTROL	0x28
-#define  SDHCI_CTRL_LED		0x01
-#define  SDHCI_CTRL_4BITBUS	0x02
-#define  SDHCI_CTRL_HISPD	0x04
-#define  SDHCI_CTRL_DMA_MASK	0x18
-#define   SDHCI_CTRL_SDMA	0x00
-#define   SDHCI_CTRL_ADMA1	0x08
-#define   SDHCI_CTRL_ADMA32	0x10
-#define   SDHCI_CTRL_ADMA64	0x18
-#define  SDHCI_CTRL_8BITBUS	0x20
-#define  SDHCI_CTRL_CD_TEST_INS	0x40
-#define  SDHCI_CTRL_CD_TEST	0x80
-
-#define SDHCI_POWER_CONTROL	0x29
-#define  SDHCI_POWER_ON		0x01
-#define  SDHCI_POWER_180	0x0A
-#define  SDHCI_POWER_300	0x0C
-#define  SDHCI_POWER_330	0x0E
-
-#define SDHCI_BLOCK_GAP_CONTROL	0x2A
-
-#define SDHCI_WAKE_UP_CONTROL	0x2B
-#define  SDHCI_WAKE_ON_INT	0x01
-#define  SDHCI_WAKE_ON_INSERT	0x02
-#define  SDHCI_WAKE_ON_REMOVE	0x04
-
-#define SDHCI_CLOCK_CONTROL	0x2C
-#define  SDHCI_DIVIDER_SHIFT	8
-#define  SDHCI_DIVIDER_HI_SHIFT	6
-#define  SDHCI_DIV_MASK	0xFF
-#define  SDHCI_DIV_MASK_LEN	8
-#define  SDHCI_DIV_HI_MASK	0x300
-#define  SDHCI_CLOCK_CARD_EN	0x0004
-#define  SDHCI_CLOCK_INT_STABLE	0x0002
-#define  SDHCI_CLOCK_INT_EN	0x0001
-
-#define SDHCI_TIMEOUT_CONTROL	0x2E
-
-#define SDHCI_SOFTWARE_RESET	0x2F
-#define  SDHCI_RESET_ALL	0x01
-#define  SDHCI_RESET_CMD	0x02
-#define  SDHCI_RESET_DATA	0x04
-
-#define SDHCI_INT_STATUS	0x30
-#define SDHCI_INT_ENABLE	0x34
-#define SDHCI_SIGNAL_ENABLE	0x38
-#define  SDHCI_INT_RESPONSE	0x00000001
-#define  SDHCI_INT_DATA_END	0x00000002
-#define  SDHCI_INT_DMA_END	0x00000008
-#define  SDHCI_INT_SPACE_AVAIL	0x00000010
-#define  SDHCI_INT_DATA_AVAIL	0x00000020
-#define  SDHCI_INT_CARD_INSERT	0x00000040
-#define  SDHCI_INT_CARD_REMOVE	0x00000080
-#define  SDHCI_INT_CARD_INT	0x00000100
-#define  SDHCI_INT_ERROR	0x00008000
-#define  SDHCI_INT_TIMEOUT	0x00010000
-#define  SDHCI_INT_CRC		0x00020000
-#define  SDHCI_INT_END_BIT	0x00040000
-#define  SDHCI_INT_INDEX	0x00080000
-#define  SDHCI_INT_DATA_TIMEOUT	0x00100000
-#define  SDHCI_INT_DATA_CRC	0x00200000
-#define  SDHCI_INT_DATA_END_BIT	0x00400000
-#define  SDHCI_INT_BUS_POWER	0x00800000
-#define  SDHCI_INT_ACMD12ERR	0x01000000
-#define  SDHCI_INT_ADMA_ERROR	0x02000000
-
-#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
-#define  SDHCI_INT_ERROR_MASK	0xFFFF8000
-
-#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT \
-				| SDHCI_INT_CRC | SDHCI_INT_END_BIT \
-				| SDHCI_INT_INDEX)
-#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END \
-				| SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL \
-				| SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC \
-				| SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
-#define SDHCI_INT_ALL_MASK	((unsigned int)-1)
-
-#define SDHCI_ACMD12_ERR	0x3C
-
-#define SDHCI_HOST_CONTROL2             0x3E
-#define  SDHCI_CTRL_UHS_MASK            0x0007
-#define   SDHCI_CTRL_UHS_SDR12          0x0000
-#define   SDHCI_CTRL_UHS_SDR25          0x0001
-#define   SDHCI_CTRL_UHS_SDR50          0x0002
-#define   SDHCI_CTRL_UHS_SDR104         0x0003
-#define   SDHCI_CTRL_UHS_DDR50          0x0004
-#define   SDHCI_CTRL_HS400		0x0005 /* reserved value in SDIO spec */
-#define  SDHCI_CTRL_VDD_180             0x0008
-#define  SDHCI_CTRL_DRV_TYPE_MASK       0x0030
-#define   SDHCI_CTRL_DRV_TYPE_B         0x0000
-#define   SDHCI_CTRL_DRV_TYPE_A         0x0010
-#define   SDHCI_CTRL_DRV_TYPE_C         0x0020
-#define   SDHCI_CTRL_DRV_TYPE_D         0x0030
-#define  SDHCI_CTRL_EXEC_TUNING         0x0040
-#define  SDHCI_CTRL_TUNED_CLK           0x0080
-#define  SDHCI_CTRL_PRESET_VAL_ENABLE   0x8000
-
-#define SDHCI_CAPABILITIES	0x40
-#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
-#define  SDHCI_TIMEOUT_CLK_SHIFT 0
-#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
-#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
-#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
-#define  SDHCI_CLOCK_BASE_SHIFT	8
-#define  SDHCI_MAX_BLOCK_MASK	0x00030000
-#define  SDHCI_MAX_BLOCK_SHIFT  16
-#define  SDHCI_CAN_DO_8BIT	0x00040000
-#define  SDHCI_CAN_DO_ADMA2	0x00080000
-#define  SDHCI_CAN_DO_ADMA1	0x00100000
-#define  SDHCI_CAN_DO_HISPD	0x00200000
-#define  SDHCI_CAN_DO_SDMA	0x00400000
-#define  SDHCI_CAN_VDD_330	0x01000000
-#define  SDHCI_CAN_VDD_300	0x02000000
-#define  SDHCI_CAN_VDD_180	0x04000000
-#define  SDHCI_CAN_64BIT	0x10000000
-
-#define SDHCI_CAPABILITIES_1	0x44
-#define SDHCI_SUPPORT_HS400	0x80000000
-
-#define SDHCI_MAX_CURRENT	0x48
-
-/* 4C-4F reserved for more max current */
-
-#define SDHCI_SET_ACMD12_ERROR	0x50
-#define SDHCI_SET_INT_ERROR	0x52
-
-#define SDHCI_ADMA_ERROR	0x54
-
-/* 55-57 reserved */
-
-#define SDHCI_ADMA_ADDRESS	0x58
-
-/* 60-FB reserved */
-
-#define SDHCI_SLOT_INT_STATUS	0xFC
-
-#define SDHCI_HOST_VERSION	0xFE
-#define  SDHCI_VENDOR_VER_MASK	0xFF00
-#define  SDHCI_VENDOR_VER_SHIFT	8
-#define  SDHCI_SPEC_VER_MASK	0x00FF
-#define  SDHCI_SPEC_VER_SHIFT	0
-#define   SDHCI_SPEC_100	0
-#define   SDHCI_SPEC_200	1
-#define   SDHCI_SPEC_300	2
-
-/*
- * End of controller registers.
- */
-
-#define SDHCI_MAX_DIV_SPEC_200	256
-#define SDHCI_MAX_DIV_SPEC_300	2046
-
-/*
- * Controller SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
- */
-#define SDHCI_DEFAULT_BOUNDARY_SIZE	(512 * 1024)
-#define SDHCI_DEFAULT_BOUNDARY_ARG	(7)
-
-#define SDHCI_MAX_PER_DESCRIPTOR 0x10000
-
-/* ADMA descriptor attributes */
-#define SDHCI_ADMA_VALID (1 << 0)
-#define SDHCI_ADMA_END (1 << 1)
-#define SDHCI_ADMA_INT (1 << 2)
-#define SDHCI_ACT_NOP (0 << 4)
-#define SDHCI_ACT_TRAN (2 << 4)
-#define SDHCI_ACT_LINK (3 << 4)
-
-static inline void sdhci_writel(struct sdhci_ctrlr *sdhci_ctrlr, u32 val,
-	int reg)
-{
-	write32(sdhci_ctrlr->ioaddr + reg, val);
-}
-
-static inline void sdhci_writew(struct sdhci_ctrlr *sdhci_ctrlr, u16 val,
-	int reg)
-{
-	write16(sdhci_ctrlr->ioaddr + reg, val);
-}
-
-static inline void sdhci_writeb(struct sdhci_ctrlr *sdhci_ctrlr, u8 val,
-	int reg)
-{
-	write8(sdhci_ctrlr->ioaddr + reg, val);
-}
-static inline u32 sdhci_readl(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
-{
-	return read32(sdhci_ctrlr->ioaddr + reg);
-}
-
-static inline u16 sdhci_readw(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
-{
-	return read16(sdhci_ctrlr->ioaddr + reg);
-}
-
-static inline u8 sdhci_readb(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
-{
-	return read8(sdhci_ctrlr->ioaddr + reg);
-}
-
-void sdhci_reset(struct sdhci_ctrlr *sdhci_ctrlr, u8 mask);
-void sdhci_cmd_done(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_command *cmd);
-int sdhci_setup_adma(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_data *data);
-int sdhci_complete_adma(struct sdhci_ctrlr *sdhci_ctrlr,
-	struct mmc_command *cmd);
-
-#endif /* __DRIVERS_STORAGE_SDHCI_H__ */