summaryrefslogtreecommitdiff
path: root/src/drivers/spi/adesto.c
diff options
context:
space:
mode:
authorSaurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>2024-07-04 19:55:56 +0530
committerFelix Held <felix-coreboot@felixheld.de>2024-08-11 17:35:27 +0000
commitde56d38b07b6f17d09286e5e77c0b6cf909ebe08 (patch)
tree0b5ed8afcc341e26c015e78b9ef9d70b91b50176 /src/drivers/spi/adesto.c
parent5bc6bd4c41591b9b322436519275dfadd5096474 (diff)
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes: 1. Add required Pather Lake SoC programming till bootblock. 2. Include only required headers into include/soc. 3. Include PTL related DID, BDF. 4. Includes additional minimal code required to compile the PTL SoC and google/fatcat mainbaord. 5. Ref: Processor EDS documents vol0.51 #815002 BUG=b:348678529 TEST=Verified on IntelĀ® SimicsĀ® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83354 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/spi/adesto.c')
0 files changed, 0 insertions, 0 deletions