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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-11-06 17:28:40 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-11-07 12:34:13 +0000 |
| commit | 7ab5dcd5c85b20804220af33fab35a550a762d87 (patch) | |
| tree | 0f042268c9b2616dd8eb9ea9a6569ae5237d8532 /src/drivers/spi/adesto.c | |
| parent | a39aedec9d5d41a5a0d8f4b709b2cad99ff05677 (diff) | |
siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY
For internal measurements this mainboard needs a marking inside the NC
FPGA when coreboot is ready and payload has been loaded.
Change-Id: I37908b21e2a077dec7fa99b0db6d1fd9b6878341
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/spi/adesto.c')
0 files changed, 0 insertions, 0 deletions