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authorArthur Heymans <arthur@aheymans.xyz>2017-12-16 22:56:19 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-05-14 07:40:08 +0000
commit701da39fb7ab9c32e3885c5428b1ee28c6ca5e04 (patch)
treeb13c108016a23a47b15ffe6340f54e01da3ed0f3 /src/drivers/sil
parentc09840020b55709f6f4e4857f6bad2fb0ff300d2 (diff)
nb/intel/x4x/raminit: Fix programming dual channel registers
Some things in programming registers related to dual channel interleaved operation were wrong. This also adds some code that could in the future be used when me is active and claims some memory for its UMA. This also uses some more sensible variable names to clarify at least some of the magic. This fixes memtest86+ failing with some assymetric DIMM configuration. TESTED on DG43GT: memtest86+ now succeeds on many more different DIMM configuration setups (would instantly fail at addresses above 4G on many configurations). Change-Id: If84099d27100e57437bf214dc4cf975f67c2ea1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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