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| author | Varshit Pandya <varshit.b.pandya@intel.com> | 2021-01-18 09:44:35 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-22 14:26:44 +0000 |
| commit | b5df56f6f20d075a86267cc3a00f2ff818ea1bc2 (patch) | |
| tree | aed06ed667eff48ceb7298fdaacc265824e591dc /src/drivers/sil | |
| parent | f4d98fdd20bbe3981684d32d3d3b257ab81163bb (diff) | |
soc/intel/alderlake: Adding Kconfig for ADL_M PCH
1. Add SOC_INTEL_ALDERLAKE_PCH_M option in Kconfig
2. Select number of I/O based on PCH
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I38783595e4b85abf5b3bec234ba01667bd9ba754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49630
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/sil')
0 files changed, 0 insertions, 0 deletions