nb/intel/x4x/raminit: Fix programming dual channel registers

Some things in programming registers related to dual channel
interleaved operation were wrong.

This also adds some code that could in the future be used when me is
active and claims some memory for its UMA.

This also uses some more sensible variable names to clarify at least
some of the magic.

This fixes memtest86+ failing with some assymetric DIMM configuration.

TESTED on DG43GT: memtest86+ now succeeds on many more different DIMM
configuration setups (would instantly fail at addresses above 4G on
many configurations).

Change-Id: If84099d27100e57437bf214dc4cf975f67c2ea1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

0 files changed, 0 insertions, 0 deletions