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author | Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> | 2021-07-09 18:36:27 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2021-07-24 15:18:43 +0000 |
commit | 3c3d2cf77fc96a789d51c58be626a8657d4650ad (patch) | |
tree | 3fd90e05366d11d07d8956c7b2abacf812936957 /src/drivers/siemens/nc_fpga | |
parent | 9bf4293c3ff5acab0542e73fc31d580446a73398 (diff) |
src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
This is in preparation for migrating EDK2 to more recent version(s). In
EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0
header (FspMultiPhaseSiInitEntryOffset). This increases the length of
the header from 72 to 76. Instead of checking for exact length check
reported header length against known minimum length for a given FSP
version.
BUG=b:180186886
TEST=build/boot with both header flavors
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/siemens/nc_fpga')
0 files changed, 0 insertions, 0 deletions