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authorFred Reitberger <reitbergerfred@gmail.com>2022-02-02 13:30:18 -0500
committerFelix Held <felix-coreboot@felixheld.de>2022-02-09 20:24:31 +0000
commit1e25fd426ad848f79e7ee7f7de4d3dc3ca129b1f (patch)
treef30379c755bfd3fd7fefa1571c73737223d547d4 /src/drivers/pcie
parent4b38a0b860ff154504598bdc94ddfda6f28f06d9 (diff)
soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION
On systems that use the first 128kByte of the SPI flash for the EC firmware, it is not possible to place the EFS/amdfw part at the lowest location in flash where the on-chip PSP firmware will look for the EFS, since this is at an offset of 128kByte into the flash which is where the cbfs master header resides when the main CBFS is placed right after the EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION option that allows putting the EFS in a separate FMAP section that can be located right after the EC firmware FMAP section. The EFS FMAP partition is checked to ensure it begins at the expected location. Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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