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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-02-17 19:37:52 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-03-04 15:22:08 +0100 |
commit | 3ee1668ab4fbf75b256ac8eef4273b1ea445c998 (patch) | |
tree | 59f35a43b85c5da6a0d9d38aba7f391971cbc980 /src/drivers/oxford/oxpcie | |
parent | c76b3d6cca4a6135e5a7d7f3c2d9aa5128ef23f0 (diff) |
uart8250: Fix and unify baudrate divisor calculation
Divisor is a function of requested baudrate, platform-specific
reference clock and amount of oversampling done on the UART reference.
Calculate this parameter with divisor rounded to nearest integer.
When building without option_table or when there is no entry for
baud_rate, CONFIG_TTYS0_BAUD is used for default baudrate.
For OxPCIe use of 4 MHz for reference was arbitrary giving correct
divisor for 115200 but somewhat inaccurate for lower baudrates.
Actual hardware is 62500000 with 16 times oversampling.
FIXME: Field for baudrate in lb_tables is still incorrect.
Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5229
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/drivers/oxford/oxpcie')
-rw-r--r-- | src/drivers/oxford/oxpcie/oxpcie_early.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d04e9d4df0..4f6f9649f5 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> +#include <uart.h> #include <uart8250.h> #include <device/pci_def.h> @@ -116,7 +117,14 @@ void oxford_init(void) /* Now the UART initialization */ u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; - uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); + unsigned int div = uart_baudrate_divisor(default_baudrate(), + uart_platform_refclk(), 16); + uart8250_mem_init(uart0_base, div); } #endif + +unsigned int uart_platform_refclk(void) +{ + return 62500000; +} |