diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-08-04 14:49:00 -0700 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-14 21:13:33 +0000 |
| commit | f48f1fdc84098ab3055d88f79fae7d3f88f13428 (patch) | |
| tree | 08be440ba6236349c8a00ae9a00a8d9661a5de33 /src/drivers/nxp/uwb/Kconfig | |
| parent | 9e111f285320a5c66bcd0f7a307ea5a25a466571 (diff) | |
drivers/nxp/uwb: Add new driver for NXP UWB SR1xx chip
Add a new driver for NXP UWB SR1xx (e.g., SR150) device.
The driver was originally written by Tim Wawrzynczak as a WIP in
CL:3503703, and was based on drivers/spi/acpi.
BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=On ghost (with follow-up CL), patch linux with NXP's pending
drivers
-> UWB device is probed and can respond to a simple hello
packet
Co-authored-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I5b1b0a5c1b48d0b09e7ab5f2ea6b6bc2fba2a7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66466
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/nxp/uwb/Kconfig')
| -rw-r--r-- | src/drivers/nxp/uwb/Kconfig | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/drivers/nxp/uwb/Kconfig b/src/drivers/nxp/uwb/Kconfig new file mode 100644 index 0000000000..01c82d1bae --- /dev/null +++ b/src/drivers/nxp/uwb/Kconfig @@ -0,0 +1,30 @@ +config DRIVERS_NXP_UWB_SR1XX + bool "NXP UWB SR1xx driver" + help + Enable support for a NXP UWB SR1xx (e.g., SR150) chip. + + A configuration should be added to device tree like below: + device ref gspi0 on + chip drivers/nxp/uwb + # The ACPI name of the device. Note it will be + # truncated to 4 characters if a longer name is given. + register "name" = ""UWB0"" + + # Description of the module. + register "desc" = ""NXP UWB Module"" + + # SPI bus speed (in Hz). + register "speed" = "1000000" + + # The GPIO connected to SENSORINT. + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_HIGH(GPP_F21)" + + # The GPIO connected to CHIP_EN. + register "ce_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A12)" + + # The GPIO connected to WAKEUP. + register "ri_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A7)" + + device spi 0 on end + end + end |