diff options
| author | Shelley Chen <shchen@google.com> | 2020-05-01 17:00:31 -0700 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2020-10-02 23:11:39 +0000 |
| commit | b4a4f59dd2cbec1cb891ea1e537591e9800df02b (patch) | |
| tree | 718dd24cb47d2ec6596e73dd86e8712c23e19eae /src/drivers/mrc_cache/Kconfig | |
| parent | 156bc6f47a7c4536649f79ee037c7eed063d1805 (diff) | |
mrc_cache: Update mrc_cache data in romstage
Previously, we were writing to cbmem after memory training and then
writing the training data from cbmem to mrc_cache in ramstage. We
were doing this because we were unable to read/write to SPI
simultaneously on older x86 chips. Now that newer chips allow for
simultaneously reads and writes, we can move the mrc_cache update into
romstage. This is beneficial if there is a reboot for some reason
after memory training but before the previous mrc_cache_stash_data
call originally in ramstage. If this happens, we would lose all the
mrc_cache training data in the next boot even though we've already
performed the memory training.
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't do mmapping but still want to use the
cbmem to store the mrc_cache data in order to write the mrc_cache data
back at a later time. We are maintaining the use of cbmem for these
older platforms because we have no way of validating the earlier write
back to mrc_cache at this time.
BUG=b:150502246
BRANCH=None
TEST=reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44196
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/mrc_cache/Kconfig')
| -rw-r--r-- | src/drivers/mrc_cache/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index 79cc205a9d..e09c5d8859 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -35,4 +35,18 @@ config MRC_WRITE_NV_LATE normal, select this item. This will cause the write to occur at BS_OS_RESUME_CHECK-ENTRY. +config MRC_STASH_TO_CBMEM + bool + default y if MRC_WRITE_NV_LATE || BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + default n + help + Instead of writing back MRC_CACHE training data back to the + MRC_CACHE right away, stash the data into cbmem. This data + will be written back later to MRC_CACHE. This is selected + for platforms which either do not support writes to SPI + flash in early stages + (BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES) or the platforms + that need to write back the MRC data in late ramstage boot + states (MRC_WRITE_NV_LATE). + endif # CACHE_MRC_SETTINGS |