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authorFelix Held <felix-coreboot@felixheld.de>2024-03-18 21:08:25 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-03-22 21:49:41 +0000
commit4b187551d202039189c2f81b56836409c002f23d (patch)
tree79c6302dd471e4a0daadca5039fed275fb444e2e /src/drivers/maxim
parent15784f1b03ee3bdcea180efd9bf47168aa452ddb (diff)
vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chip
Move the gpp_bridge_* device functions that are bridges to the external PCIe ports below the corresponding mpio chip. This avoids the need for dummy devices and does things in a slightly more coreboot-native way. TEST=PCIe lane config reported by openSIL is identical Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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