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authorGabe Black <gabeblack@google.com>2014-04-07 01:19:27 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-12-15 19:58:43 +0100
commit92dfa9c5814e7f0bb7830166a2fd7f2f04e336cb (patch)
treea4eea9b193b3dcd46d086920868048e7ca32e55d /src/drivers/maxim
parent9d32739baaf86e845436aec6c43580c5626d3499 (diff)
nyan*: Reduce the EC SPI bus frequency to 3 MHz.
The EC doesn't seem to be able to handle its bus running at 4 MHz or higher. To avoid it not being able to keep up, we reduce the frequency of that bus on all nyan derivatives to 3 MHz. Because PLLP can't be divided that low, we switch the clock source to CLKM. BUG=chrome-os-partner:22849 TEST=Built and booted on nyan. BRANCH=None Original-Change-Id: I8f31b41098d64634427b4686f5333012f643fada Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193349 Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c215c50a5bb982b0e671c951e2fe8df06db85db2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia60513d118aed8881927e9d52f170e27655ea8e7 Reviewed-on: http://review.coreboot.org/7739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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