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authorStefan Reinauer <reinauer@chromium.org>2012-07-10 13:24:29 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-07-25 01:17:26 +0200
commit8d32b89fa4ea30aa57b578d79bc656c9e6545795 (patch)
treecb98f55e18c57ad4893768aaf977623d356c5280 /src/drivers/ipmi
parentf4d362339f4d96657be1dc5956c34278d1089eba (diff)
Fix LAPIC timer on Ivy Bridge systems
The LAPIC timer is running at BCLK (100MHz) on Sandy Bridge and Ivy Bridge systems. However, the current timer code assumed that the clock would run at 200MHz instead. This made all delays twice as long as needed. Change-Id: I41b1186daee11cfd9a25b3a9d5ebdeeb271293c7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1330 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/drivers/ipmi')
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