drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs

This patch refactors the existing MRC cache storing logic, which was
spread between the ROM and RAM stages, into a single early MRC cache
store stage. The only exception is when SoC user selects
FSP_NVS_DATA_POST_SILICON_INIT to store MRC cache from ramstage (after
FSP-S).

It reverts all the boot-state logic previously used to locate and store
MRC cache from NVS HOB into NVS because majority of the platform can
potentially use the early MRC cache store with improved memory caching
at the pre-RAM phase (with the ramtop implementation).

The only exception is the Xeon SP platform, which currently locates
the MRC cache post in FSP-S (at ramstage). Therefore, this patch
provides an API to the FSP 2.x silicon init code to perform late
storing of the MRC cache.

In majority cases the updated logic, the romstage (post FSP-M) will
attempt to save the MRC cache. Platform that selects
FSP_NVS_DATA_POST_SILICON_INIT config performs the same operation post
FSP-S. Depending on whether the MRC_STASH_TO_CBMEM config is
enabled, the MRC cache will either be written directly to NVRAM at the
romstage or stashed into CBMEM for a late NVRAM write at ramstage.

Below table captures the change in the boot state w/ and w/o this
patch for storing the MRC cache. Overall the goal is to ensure the
platform behavior is remain unchanged before and after this patch.

w/o this patch:

|           | Save MRC       | Finalize       | Lock the       |
|           | Cache          | MRC Cache      | Boot Medium    |
+-----------+----------------+----------------+----------------+
| MRC_WRITE | BS_OS_RESUME   | BS_OS_RESUME   | BS_ON_RESUME   |
| NV_LATE   | CHECK_ENTRY    | CHECK_ENTRY    | CHECK_EXIT     |
+-----------+----------------+----------------+----------------+
| MRC_STASH | BS_DEV         | BS_DEV         | BS_DEV         |
| TO_CBMEM  | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY|
+-----------+----------------+----------------+----------------+
| FSP_NVS   | BS_DEV_INIT    | BS_DEV         | BS_DEV         |
| DATA_POST | CHIPS_EXIT     | ENUMERATE_EXIT | RESOURCES_ENTRY|
| SILICON   |                |                |                |
| INIT      |                |                |                |
+-----------+----------------+----------------+----------------+
| Platform  | BS_PRE         | BS_DEV         | BS_DEV         |
| w/o above | DEVICE_ENTRY   | ENUMERATE_EXIT | ENUMERATE_ENTRY|
| config    |                |                |                |
| (FSP 2.0  |                |                |                |
| platforms |                |                |                |

w/ this patch:

|           | Save MRC       | Finalize       | Lock the       |
|           | Cache          | MRC Cache      | Boot Medium    |
+-----------+----------------+----------------+----------------+
| MRC_WRITE | BS_OS_RESUME   | BS_OS_RESUME   | BS_ON_RESUME   |
| NV_LATE   | CHECK_ENTRY    | CHECK_ENTRY    | CHECK_EXIT     |
+-----------+----------------+----------------+----------------+
| MRC_STASH | BS_DEV         | BS_DEV         | BS_DEV         |
| TO_CBMEM  | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY|
+-----------+----------------+----------------+----------------+
| FSP_NVS   | Post FSP-S     | BS_DEV         | BS_DEV         |
| DATA_POST | (ramstage)     | ENUMERATE_EXIT | RESOURCES_ENTRY|
| SILICON   |                |                |                |
| INIT      |                |                |                |
+-----------+----------------+----------------+----------------+
| Platform  | Post FSP-M     | BS_DEV         | BS_DEV         |
| w/o above | (romstage)     | ENUMERATE_EXIT | ENUMERATE_ENTRY|
| config    |                |                |                |
| (FSP 2.0  |                |                |                |
| platforms |                |                |                |

BUG=b:296704537
TEST=Able to build and boot google/rex without any boot time impact.

Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77556
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

4 files changed, 11 insertions, 14 deletions

diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 756ba1ec5a..16742fd1a4 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -16,6 +16,7 @@ romstage-y += memory_init.c
 romstage-$(CONFIG_MMA) += mma_core.c
 romstage-y += cbmem.c
 romstage-$(CONFIG_ENABLE_FSP_ERROR_INFO) += fsp_error_info_hob.c
+romstage-$(CONFIG_CACHE_MRC_SETTINGS) += save_mrc_data.c
 
 ramstage-y += debug.c
 ramstage-$(CONFIG_FSP_USES_CB_DEBUG_EVENT_HANDLER) += fsp_debug_event.c
@@ -30,7 +31,7 @@ ramstage-y += notify.c
 ramstage-y += silicon_init.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 ramstage-y += util.c
-ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += save_mrc_data.c
+ramstage-$(CONFIG_FSP_NVS_DATA_POST_SILICON_INIT) += save_mrc_data.c
 ramstage-$(CONFIG_MMA) += mma_core.c
 ramstage-$(CONFIG_ENABLE_FSP_ERROR_INFO) += fsp_error_info_hob.c
 ramstage-$(CONFIG_BMP_LOGO) += fsp_gop_blt.c
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index d6677b4732..4706dce813 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -74,8 +74,11 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t version)
 		(uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY))
 		die("Failed to accommodate FSP reserved memory request!\n");
 
-	if (CONFIG(CACHE_MRC_SETTINGS) && !s3wake)
+	if (CONFIG(CACHE_MRC_SETTINGS) && !s3wake) {
 		do_cbmem_version_entry(cbmem_id, version);
+		if (!CONFIG(FSP_NVS_DATA_POST_SILICON_INIT))
+			save_memory_training_data();
+	}
 
 	/* Create romstage handof information */
 	romstage_handoff_init(s3wake);
diff --git a/src/drivers/intel/fsp2_0/save_mrc_data.c b/src/drivers/intel/fsp2_0/save_mrc_data.c
index 1d682b99c2..50be10b90c 100644
--- a/src/drivers/intel/fsp2_0/save_mrc_data.c
+++ b/src/drivers/intel/fsp2_0/save_mrc_data.c
@@ -1,13 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <acpi/acpi.h>
-#include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <mrc_cache.h>
 
-static void save_mrc_data(void *unused)
+void save_memory_training_data(void)
 {
 	size_t mrc_data_size;
 	const void *mrc_data;
@@ -41,13 +40,3 @@ static void save_mrc_data(void *unused)
 				 mrc_data_size) < 0)
 		printk(BIOS_ERR, "Failed to stash MRC data\n");
 }
-
-/*
- * Should be done before ramstage_cse_fw_sync() to avoid traning memory twice on
- * a cold boot after a full firmware update.
- */
-#if CONFIG(FSP_NVS_DATA_POST_SILICON_INIT)
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, save_mrc_data, NULL);
-#else
-BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, save_mrc_data, NULL);
-#endif
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 72a30c51e3..094eed4160 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -9,6 +9,7 @@
 #include <console/console.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
+#include <mrc_cache.h>
 #include <program_loading.h>
 #include <soc/intel/common/reset.h>
 #include <soc/intel/common/vbt.h>
@@ -253,6 +254,9 @@ void fsp_silicon_init(void)
 	fsps_load();
 	do_silicon_init(&fsps_hdr);
 
+	if (CONFIG(CACHE_MRC_SETTINGS) && CONFIG(FSP_NVS_DATA_POST_SILICON_INIT))
+		save_memory_training_data();
+
 	if (CONFIG(DISPLAY_FSP_TIMESTAMPS))
 		fsp_display_timestamp();
 }