diff options
| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2018-02-27 19:40:52 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-04 20:33:07 +0000 |
| commit | c07f8fbe6fd13e4245da71574b52b47e9733db84 (patch) | |
| tree | 12db8b3c40552eab81045c6165538e2d3ba36ce8 /src/drivers/intel | |
| parent | 961d31bdb3c97e177156ed335d6f2c726d08ab51 (diff) | |
security/tpm: Unify the coreboot TPM software stack
* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp1_1/romstage.c | 6 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 2 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/memory_init.c | 9 |
3 files changed, 9 insertions, 8 deletions
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index ba08cdc42b..0320bf5724 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -37,7 +37,7 @@ #include <stage_cache.h> #include <string.h> #include <timestamp.h> -#include <security/tpm/tis.h> +#include <security/tpm/tspi.h> #include <vendorcode/google/chromeos/chromeos.h> asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) @@ -172,9 +172,9 @@ void romstage_common(struct romstage_params *params) * Initialize the TPM, unless the TPM was already initialized * in verstage and used to verify romstage. */ - if (IS_ENABLED(CONFIG_LPC_TPM) && + if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) && !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) - init_tpm(params->power_state->prev_sleep_state == + tpm_setup(params->power_state->prev_sleep_state == ACPI_S3); } diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 1ff8aa68ef..f14954463b 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -119,6 +119,8 @@ config DISPLAY_FSP_VERSION_INFO config FSP2_0_USES_TPM_MRC_HASH bool + depends on TPM1 || TPM2 + depends on VBOOT default y if HAS_RECOVERY_MRC_CACHE default n select VBOOT_HAS_REC_HASH_SPACE diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 30987ce500..1ca52085a7 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -12,7 +12,7 @@ */ #include <compiler.h> -#include <security/tpm/antirollback.h> +#include <security/vboot/antirollback.h> #include <arch/io.h> #include <arch/cpu.h> #include <arch/symbols.h> @@ -31,8 +31,7 @@ #include <string.h> #include <symbols.h> #include <timestamp.h> -#include <security/tpm/tis.h> -#include <security/tpm/tss.h> +#include <security/tpm/tspi.h> #include <security/vboot/vboot_common.h> #include <vb2_api.h> @@ -152,9 +151,9 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) * Initialize the TPM, unless the TPM was already initialized * in verstage and used to verify romstage. */ - if (IS_ENABLED(CONFIG_LPC_TPM) && + if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) && !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) - init_tpm(s3wake); + tpm_setup(s3wake); } static int mrc_cache_verify_tpm_hash(const uint8_t *data, size_t size) |