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authorNico Huber <nico.h@gmx.de>2018-08-23 21:52:05 +0200
committerMartin Roth <martinroth@google.com>2018-08-30 14:45:50 +0000
commit58344fc2e7d9256524997b5aecd6130534c6702c (patch)
treed159cec418e471109035001a06ea38fd5528ccf0 /src/drivers/intel
parent661907cdb4eda6c3d0044895b4cccfc10b6bd8ac (diff)
drivers/intel/gma: Fix OpRegion Mailbox3 backlight change
We should always update BCLP, no matter if the driver is ready yet to process the request. This way it will hold the current value when the driver initializes. Change-Id: I4b091d744f95da39abe542966f0a8589a187573b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/gma/acpi/configure_brightness_levels.asl15
1 files changed, 9 insertions, 6 deletions
diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
index 0867c5ae06..01642ddc6b 100644
--- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
+++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Nico Huber <nico.huber@secunet.com>
+ * Copyright (C) 2018 Nico Huber <nico.h@gmx.de>
* Copyright (C) 2018 Patrick Rudolph
*
* This program is free software; you can redistribute it and/or modify
@@ -64,19 +65,21 @@
{
Return (Ones)
}
- If (LEqual(ARDY, Zero))
- {
- Return (Ones)
- }
- /* BCLP requires brightness unsigned 8bit. 255 = 100 % */
+ /* Always keep BCLP up to date, even if driver is not ready.
+ It requires a full 8-bit brightness value. 255 = 100% */
Store (Divide (Multiply (Arg0, 255), 100), Local1)
If (LGreater(Local1, 255)) {
Store (255, Local1)
}
- /* set valid bit */
+ /* also set valid bit */
Store (Or (Local1, 0x80000000), BCLP)
+ If (LEqual(ARDY, Zero))
+ {
+ Return (Ones)
+ }
+
/* Request back-light change */
Store (0x2, ASLC)
/* Trigger IRQ */