diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-08-24 14:58:12 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-25 22:50:17 +0200 |
| commit | f7ce40baf6a26e70ca18026f26977cd7f6f2cefa (patch) | |
| tree | e8b942f64f1a45e96f8406e70c958f8b561dec2e /src/drivers/intel | |
| parent | 70385968cea517ed20dc3f3f665d92096acc768c (diff) | |
vboot: consolidate google_chromeec_early_init() calls
On x86 platforms, google_chromeec_early_init() is used to put the EC
into RO mode when there's a recovery request. This is to avoid training
memory multiple times when the recovery request is through an EC host
event while the EC is running RW code. Under that condition the EC will
be reset (along with the rest of the system) when the kernel verification
happens. This leads to an execessively long recovery path because of the
double reboot performing full memory training each time.
By putting this logic into the verstage program this reduces the
bootblock size on the skylake boards. Additionally, this provides the
the correct logic for all future boards since it's not tied to FSP
nor the mainboard itself. Lastly, this double memory training protection
works only for platforms which verify starting from bootblock. The
platforms which don't start verifying until after romstage need to
have their own calls (such as haswell and baytrail).
Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16318
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp1_1/car.c | 6 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/memory_init.c | 9 |
2 files changed, 0 insertions, 15 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 7eceebf5ba..1a5f9a8333 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -15,7 +15,6 @@ #include <arch/early_variables.h> #include <console/console.h> -#include <ec/google/chromeec/ec.h> #include <fsp/car.h> #include <fsp/util.h> #include <program_loading.h> @@ -62,11 +61,6 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) car_soc_post_console_init(); car_mainboard_post_console_init(); - /* Ensure the EC is in the right mode for recovery */ - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) && - !IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) - google_chromeec_early_init(); - set_fih_car(car_params->fih); /* Return new stack value in RAM back to assembly stub. */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index e545b6d155..1957cdb952 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -17,7 +17,6 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <ec/google/chromeec/ec.h> #include <elog.h> #include <fsp/api.h> #include <fsp/util.h> @@ -296,14 +295,6 @@ void fsp_memory_init(bool s3wake) if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake) boot_count_increment(); - /* - * Before doing any memory init/training, ensure that the EC is in the - * right mode. This saves an additional memory training when in recovery - * mode. - */ - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) - google_chromeec_early_init(); - if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); die("FSPM not available!\n"); |