src/drivers: Fix typo

Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27916
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 7 insertions, 7 deletions

diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index 51f9a75373..0f13efe424 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -128,7 +128,7 @@ void romstage_common(struct romstage_params *params)
 			params->pei_data->saved_data_size =
 				region_device_sz(&rdev);
 			params->pei_data->saved_data = rdev_mmap_full(&rdev);
-			/* Assum boot device is memory mapped. */
+			/* Assume boot device is memory mapped. */
 			assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
 		} else if (params->pei_data->boot_mode == ACPI_S3) {
 			/* Waking from S3 and no cache. */
diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c
index f36f6de475..8f4dc1ea9b 100644
--- a/src/drivers/intel/fsp2_0/debug.c
+++ b/src/drivers/intel/fsp2_0/debug.c
@@ -36,7 +36,7 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
 	if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
 		fspm_display_upd_values(fspm_old_upd, fspm_new_upd);
 
-	/* Display the call entry point and paramters */
+	/* Display the call entry point and parameters */
 	if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
 		return;
 	printk(BIOS_SPEW, "Calling FspMemoryInit: 0x%p\n", memory_init);
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 123db303ca..5ed3801851 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -107,7 +107,7 @@ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
  *
  * This function is responsible for loading and executing the notify code from
  * the FSP-S binary. It expects that fsp_silicon_init() has already been called
- * succesfully, and that the FSP-S binary is still loaded into memory.
+ * successfully, and that the FSP-S binary is still loaded into memory.
  */
 
 #endif /* _FSP2_0_API_H_ */
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h
index ae774a549e..e0bf1427c5 100644
--- a/src/drivers/intel/gma/i915_reg.h
+++ b/src/drivers/intel/gma/i915_reg.h
@@ -609,7 +609,7 @@
 #define LM_FIFO_WATERMARK   0x0000001F
 #define MI_ARB_STATE	0x020e4 /* 915+ only */
 
-/* Make render/texture TLB fetches lower priorty than associated data
+/* Make render/texture TLB fetches lower priority than associated data
  *   fetches. This is not turned on by default
  */
 #define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
@@ -1636,9 +1636,9 @@
 #define   BLM_PIPE_C			(2 << 29) /* ivb + */
 #define   BLM_PIPE(pipe)		((pipe) << 29)
 #define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
-#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
+#define   BLM_PHASE_IN_INTERRUPT_STATUS	(1 << 26)
 #define   BLM_PHASE_IN_ENABLE		(1 << 25)
-#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
+#define   BLM_PHASE_IN_INTERRUPT_ENABL	(1 << 24)
 #define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
 #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
 #define   BLM_PHASE_IN_COUNT_SHIFT	(8)
diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
index 70cbccc876..5def085908 100644
--- a/src/drivers/intel/gma/opregion.c
+++ b/src/drivers/intel/gma/opregion.c
@@ -318,7 +318,7 @@ intel_gma_init_igd_opregion(igd_opregion_t *opregion)
 	opregion->header.size = sizeof(igd_opregion_t) / 1024;
 
 	/*
-	 * Left-shift version field to accomodate Intel Windows driver quirk
+	 * Left-shift version field to accommodate Intel Windows driver quirk
 	 * when not using a VBIOS.
 	 * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver.
 	 *