diff options
| author | Martin Roth <martinroth@google.com> | 2017-06-03 20:03:18 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-06-07 12:09:15 +0200 |
| commit | e18e6427d0f3261f9ec361d4418b8fe1dd7cc469 (patch) | |
| tree | f6a10fc93dddada7e49108a5ad06e71590f2d54c /src/drivers/intel | |
| parent | e81ce0483db982c741eebdda649111eee22a853b (diff) | |
src: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/raminit.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6611fa192d..fc662082cf 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -137,7 +137,7 @@ CAR_init_done: /* Save FSP_INFO_HEADER location in ebx */ mov %ebp, %ebx - /* Coreboot assumes stack/heap region will be zero */ + /* coreboot assumes stack/heap region will be zero */ cld movl %ecx, %edi neg %ecx diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 6e2efcfabb..5b6ec9e779 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -277,7 +277,7 @@ void raminit(struct romstage_params *params) /* Verify the FSP 1.1 HOB interface */ if (fsp_verification_failure) - die("ERROR - Coreboot's requirements not met by FSP binary!\n"); + die("ERROR - coreboot's requirements not met by FSP binary!\n"); /* Display the memory configuration */ report_memory_config(); |