diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-20 14:20:53 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-06 14:01:48 +0000 |
| commit | 71bd7e439fed00c73712be4f9522f412e3ab8559 (patch) | |
| tree | f38e8a93394ed1e1b641354c30a5e63f964e82b7 /src/drivers/intel | |
| parent | aae81906b940c84b53944ec48d08074d8a0d153d (diff) | |
drivers/intel/fsp2_0: Move Debug options to "Debugging"
Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 38 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig.debug_blob | 41 |
2 files changed, 41 insertions, 38 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index b434a514a4..3403df99ae 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -37,32 +37,6 @@ config ADD_FSP_BINARIES Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not use the FSP-T binary and it is not added. -config DISPLAY_FSP_CALLS_AND_STATUS - bool "Display the FSP calls and status" - default n - help - Display the FSP call entry point and parameters prior to calling FSP - and display the status upon return from FSP. - -config DISPLAY_FSP_HEADER - bool "Display the FSP header" - default n - help - Display the FSP header information when the FSP file is found. - -config DISPLAY_HOBS - bool "Display the hand-off-blocks" - default n - help - Display the FSP HOBs which are provided for coreboot. - -config DISPLAY_UPD_DATA - bool "Display UPD data" - default n - help - Display the user specified product data prior to memory - initialization. - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" depends on FSP_CAR @@ -158,22 +132,10 @@ config FSP_TEMP_RAM_SIZE stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation. -config VERIFY_HOBS - bool "Verify the FSP hand-off-blocks" - default n - help - Verify that the HOBs required by coreboot are returned by FSP and - that the resource HOBs are in the correct order and position. - config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n -config DISPLAY_FSP_VERSION_INFO - bool "Display Firmware Ingredient Version Information" - help - Select this option to display Firmware version information. - config FSP2_0_USES_TPM_MRC_HASH bool depends on TPM1 || TPM2 diff --git a/src/drivers/intel/fsp2_0/Kconfig.debug_blob b/src/drivers/intel/fsp2_0/Kconfig.debug_blob new file mode 100644 index 0000000000..2b10c2df4f --- /dev/null +++ b/src/drivers/intel/fsp2_0/Kconfig.debug_blob @@ -0,0 +1,41 @@ +if PLATFORM_USES_FSP2_0 + +config DISPLAY_FSP_CALLS_AND_STATUS + bool "Display the FSP calls and status" + default n + help + Display the FSP call entry point and parameters prior to calling FSP + and display the status upon return from FSP. + +config DISPLAY_FSP_HEADER + bool "Display the FSP header" + default n + help + Display the FSP header information when the FSP file is found. + +config DISPLAY_HOBS + bool "Display the hand-off-blocks" + default n + help + Display the FSP HOBs which are provided for coreboot. + +config DISPLAY_UPD_DATA + bool "Display UPD data" + default n + help + Display the user specified product data prior to memory + initialization. + +config VERIFY_HOBS + bool "Verify the FSP hand-off-blocks" + default n + help + Verify that the HOBs required by coreboot are returned by FSP and + that the resource HOBs are in the correct order and position. + +config DISPLAY_FSP_VERSION_INFO + bool "Display Firmware Ingredient Version Information" + help + Select this option to display Firmware version information. + +endif # PLATFORM_USES_FSP2_0 |