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| author | Patrick Georgi <pgeorgi@google.com> | 2018-09-13 11:48:43 -0400 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-10-12 23:20:53 +0000 |
| commit | 6539e10c4f209ea4273a78528b26c1f9ff4a3047 (patch) | |
| tree | 305cfa9247a93ccb0b3db13d644f46323859cdfd /src/drivers/intel | |
| parent | f3aa6e9319dc6eaabbb16eb3d09956711a121d30 (diff) | |
drivers/intel/fsp2_0: Hook up IntelFSP repo
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using
Intel's FSP repo (that we mirror) to build a complete BIOS ifd region
with a simple coreboot build, automatically drawing in headers and
binaries.
This commit covers Apollolake, Coffeelake, Skylake, and Kabylake.
Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's
also supports Skylake.
Another candidate (given 3rdparty/fsp's content) is Denverton NS, but
it requires changes to coreboot's FSP bindings to become compatible.
Cannonlake, Whiskeylake require an FSP release.
Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28593
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 12 | ||||
| -rw-r--r-- | src/drivers/intel/fsp2_0/Makefile.inc | 15 |
2 files changed, 27 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 4c4dfb2f24..7cf4993597 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -66,21 +66,33 @@ config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" +config FSP_USE_REPO + bool "Use the IntelFSP based binaries" + depends on ADD_FSP_BINARIES + depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + help + When selecting this option, the SoC must set FSP_HEADER_PATH + and FSP_FD_PATH correctly so FSP splitting works. + config FSP_T_FILE string "Intel FSP-T (temp ram init) binary path and filename" depends on FSP_CAR + default "$(obj)/Fsp_T.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-M binary for this platform. config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES + default "$(obj)/Fsp_M.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-M binary for this platform. config FSP_S_FILE string "Intel FSP-S (silicon init) binary path and filename" depends on ADD_FSP_BINARIES + default "$(obj)/Fsp_S.fd" if FSP_USE_REPO help The path and filename of the Intel FSP-S binary for this platform. diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index d5709adc31..e85520f9d8 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -64,4 +64,19 @@ cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_S_CBFS) $(CONFIG_FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) $(CONFIG_FSP_S_CBFS)-type := fsp +ifeq ($(CONFIG_FSP_USE_REPO),y) +$(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) + python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" + +$(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd + true + +$(obj)/Fsp_T.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd + true +endif + +ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),) +CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH) +endif + endif |