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authorAaron Durbin <adurbin@chromium.org>2015-12-08 14:34:35 -0600
committerAaron Durbin <adurbin@chromium.org>2015-12-10 04:44:09 +0100
commit7e7a4df58075fdff4293d2203b035b970d21aeb8 (patch)
tree5897c05b07adaa7d12f747a49dc3f513d2dc2d9e /src/drivers/intel
parent6d720f38e06d14cc8a89635f66dc124dcd5ac150 (diff)
lib: remove assets infrastructure
Now that only CBFS access is supported for finding resources within the boot media the assets infrastructure can be removed. Remove it. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. Change-Id: I383fd6579280cf9cfe5a18c2851baf74cad004e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/drivers/intel')
-rw-r--r--src/drivers/intel/fsp1_1/car.c2
-rw-r--r--src/drivers/intel/fsp1_1/ramstage.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 23312e14cc..b525a6223e 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -79,7 +79,7 @@ asmlinkage void *romstage_after_verstage(void)
/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
* is still enabled. We can directly access work buffer here. */
FSP_INFO_HEADER *fih;
- struct prog fsp = PROG_INIT(ASSET_REFCODE, "fsp.bin");
+ struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
console_init();
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index aa1b658068..20ec323308 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -176,7 +176,7 @@ static int fsp_find_and_relocate(struct prog *fsp)
void intel_silicon_init(void)
{
- struct prog fsp = PROG_INIT(ASSET_REFCODE, "fsp.bin");
+ struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
int is_s3_wakeup = acpi_is_wakeup_s3();
if (is_s3_wakeup) {