diff options
author | Furquan Shaikh <furquan@google.com> | 2013-07-31 16:47:31 -0700 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 13:26:55 +0100 |
commit | db3157cfee6881d8095c4f96cd1fa5d5da9a5c68 (patch) | |
tree | c25d2542d6880b8a5c38fe0bc59e7553c7725a60 /src/drivers/intel/gma/intel_dp.c | |
parent | d0a81f75342508449d13fd05305864413470e0c9 (diff) |
Add cpu transcoder attribute to intel dp
Also, used this attribute in the calculation of htotal and other registers
Added intel_dp_* functions for m,n registers and dimension register calculations
Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a
Reviewed-on: https://gerrit.chromium.org/gerrit/64001
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4422
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/drivers/intel/gma/intel_dp.c')
-rw-r--r-- | src/drivers/intel/gma/intel_dp.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c index 0def7717ac..419e49ed2d 100644 --- a/src/drivers/intel/gma/intel_dp.c +++ b/src/drivers/intel/gma/intel_dp.c @@ -1739,3 +1739,25 @@ intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread) return 1; } +void intel_dp_set_m_n_regs(struct intel_dp *intel_dp) +{ + io_i915_write32(0x7e4a0000, PIPE_DATA_M1(intel_dp->transcoder)); + /* io_i915_write32(0x00800000,0x6f034); */ + /* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important. + However, with our formula we always see values 0x7e43yyyy (1366 panel) and + 0x7e42yyy (1280 panel) */ + /* io_i915_write32(TU_SIZE(intel_dp->m_n.tu) | intel_dp->m_n.gmch_m,PIPE_DATA_M1(intel_dp->transcoder)); */ + io_i915_write32(intel_dp->m_n.gmch_n, PIPE_DATA_N1(intel_dp->transcoder)); + io_i915_write32(intel_dp->m_n.link_m, PIPE_LINK_M1(intel_dp->transcoder)); + io_i915_write32(intel_dp->m_n.link_n, PIPE_LINK_N1(intel_dp->transcoder)); +} + +void intel_dp_set_resolution(struct intel_dp *intel_dp) +{ + io_i915_write32(intel_dp->htotal, HTOTAL(intel_dp->transcoder)); + io_i915_write32(intel_dp->hblank, HBLANK(intel_dp->transcoder)); + io_i915_write32(intel_dp->hsync, HSYNC(intel_dp->transcoder)); + io_i915_write32(intel_dp->vtotal, VTOTAL(intel_dp->transcoder)); + io_i915_write32(intel_dp->vblank, VBLANK(intel_dp->transcoder)); + io_i915_write32(intel_dp->vsync, VSYNC(intel_dp->transcoder)); +} |