diff options
| author | Furquan Shaikh <furquan@google.com> | 2013-08-19 10:16:50 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-13 19:32:11 +0200 |
| commit | 77f48cdeade7fc296fb5c973b6b0191ac5bd8c35 (patch) | |
| tree | d33aac05f3759fde05c29c1d43b0aaeed07c34d8 /src/drivers/intel/gma/i915_reg.h | |
| parent | 61ffb4ca2e53004d3a282bfc2c97e58131cc9ef3 (diff) | |
Falco/Slippy: Patch to refactor haswell/gma.c and mainboard/google/slippy/i915io.c
A large portion of documented registers have been initialized using macros. Only a few
undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant
calls. However, some more work is required to correctly identify which calls are not required.
All the io_writes are replaced by gtt_writes.
Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66204
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6600
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/drivers/intel/gma/i915_reg.h')
| -rw-r--r-- | src/drivers/intel/gma/i915_reg.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index cbb0628856..2ee5748e75 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -1672,6 +1672,7 @@ /* New registers for PCH-split platforms. Safe where new bits show up, the * register layout machtes with gen4 BLC_PWM_CTL[12]. */ #define BLC_PWM_CPU_CTL2 0x48250 +#define BLC_PWM2_ENABLE (1<<31) #define BLC_PWM_CPU_CTL 0x48254 #define BLM_HIST_CTL 0x48260 @@ -2978,6 +2979,7 @@ /* Ironlake */ #define CPU_VGACNTRL 0x41000 +#define CPU_VGA_DISABLE (1<<31) #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) @@ -4391,4 +4393,8 @@ #define WM_DBG_DISALLOW_MAXFIFO (1<<1) #define WM_DBG_DISALLOW_SPRITE (1<<2) +/* North Display Engine Reset Warn Options */ +#define NDE_RSTWRN_OPT 0x46408 +#define RST_PCH_HNDSHK_EN (1<<4) + #endif /* _I915_REG_H_ */ |