drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp load

Add a function to allow FSP component loading separately from silicon
initialization. This enables SoCs that might not have stage cache
available during silicon initialization to load/save components from/to
stage cache before it is relocated or destroyed.

BUG=chrome-os-partner:63114
BRANCH=None
TEST=Compiles successfully.

Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18413
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2 files changed, 19 insertions, 4 deletions

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 3b4334d804..3532ad2ef8 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -42,6 +42,13 @@ void fsp_memory_init(bool s3wake);
 void fsp_silicon_init(bool s3wake);
 void fsp_temp_ram_exit(void);
 
+/*
+ * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S
+ * separately from calling silicon init. It might be required in cases where
+ * stage cache is no longer available by the point SoC calls into silicon init.
+ */
+void fsps_load(bool s3wake);
+
 /* Callbacks for updating stage-specific parameters */
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index e6464aa3df..a57f97603e 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -62,7 +62,7 @@ static void do_silicon_init(struct fsp_header *hdr)
 	}
 }
 
-void fsp_silicon_init(bool s3wake)
+void fsps_load(bool s3wake)
 {
 	struct fsp_header *hdr = &fsps_hdr;
 	struct cbfsf file_desc;
@@ -71,17 +71,20 @@ void fsp_silicon_init(bool s3wake)
 	void *dest;
 	size_t size;
 	struct prog fsps = PROG_INIT(PROG_REFCODE, name);
+	static int load_done;
+
+	if (load_done)
+		return;
 
 	if (s3wake && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) {
 		printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n");
 		stage_cache_load_stage(STAGE_REFCODE, &fsps);
 		if (fsp_validate_component(hdr, prog_rdev(&fsps)) != CB_SUCCESS)
 			die("On resume fsps header is invalid\n");
-		do_silicon_init(hdr);
+		load_done = 1;
 		return;
 	}
 
-
 	if (cbfs_boot_locate(&file_desc, name, NULL)) {
 		printk(BIOS_ERR, "Could not locate %s in CBFS\n", name);
 		die("FSPS not available!\n");
@@ -116,6 +119,11 @@ void fsp_silicon_init(bool s3wake)
 
 	/* Signal that FSP component has been loaded. */
 	prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL);
+	load_done = 1;
+}
 
-	do_silicon_init(hdr);
+void fsp_silicon_init(bool s3wake)
+{
+	fsps_load(s3wake);
+	do_silicon_init(&fsps_hdr);
 }