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| author | zoey wu <zoey_wu@wistron.corp-partner.google.com> | 2022-03-01 17:31:50 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-10 15:13:22 +0000 |
| commit | a4b821a9af333cf9ea639cbb70e40c602d531d67 (patch) | |
| tree | 63b4df4d2a494a2c17c76acdf94d332e33633c69 /src/drivers/intel/fsp2_0 | |
| parent | 1c14957254ced5eb8cfb4f20230422d951a9ffac (diff) | |
mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4.
BUG=b:219831754
Signed-off-by: zoey wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/drivers/intel/fsp2_0')
0 files changed, 0 insertions, 0 deletions