diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-18 19:40:48 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-19 19:31:08 +0000 |
| commit | 4f14cd8a39e65811af08296633842289efa42927 (patch) | |
| tree | 1cece9915f897af008d2d83701088b3054c4ab93 /src/drivers/intel/fsp2_0 | |
| parent | 6766f4fd046604e6376c9769cd5f8357dec6a80a (diff) | |
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.
This also adds board reset for failing to load postcar
from stage cache.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp2_0')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 7ce7838642..a8b3ac43a5 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -117,10 +117,6 @@ config FSP_TEMP_RAM_SIZE stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation. -config RESET_ON_INVALID_RAMSTAGE_CACHE - bool "Reset the system on S3 wake when ramstage cache invalid." - default n - config FSP2_0_USES_TPM_MRC_HASH bool depends on TPM1 || TPM2 |